Reverse-Doped Nanostructure Memory Cells for Lower Gate Leakage
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Solution Overview
Problem
Existing anti-fuse memory devices suffer from performance and lifetime issues due to gate leakage current, which requires higher programming voltages and reduces device efficiency.
Innovation Solution
The implementation of nanostructure transistors with a floating source/drain doped in a reverse conduction type, reducing the p-n junction and subsequently minimizing gate leakage, allowing for lower programming voltages while maintaining successful programming of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional anti-fuse memory devices are used, then programming can be achieved, but gate leakage current increases requiring higher programming voltages and reducing device efficiency
Solution Approach 1:
The patent applies local quality by doping only the floating source/drain region with a reverse conduction type, while keeping other regions with their original doping types. This localized modification reduces the p-n junction area specifically at the floating source/drain, thereby minimizing gate leakage current without affecting other device regions. The selective doping approach directly addresses the energy loss issue while maintaining programming functionality.
Solution Approach 2:
The patent changes the doping type parameter of the floating source/drain from the conventional type to a reverse conduction type. This parameter change fundamentally alters the electrical characteristics of the floating source/drain region, reducing the p-n junction effect and subsequently minimizing gate leakage current. The parameter change enables lower programming voltages while maintaining successful programming.
2Reliability
If higher programming voltages are applied to overcome gate leakage, then programming can be achieved, but device lifetime is reduced
Solution Approach 1:
By locally modifying the doping type of the floating source/drain region, the patent reduces gate leakage current at the critical interface area. This localized improvement eliminates the need for higher programming voltages, thereby preserving device lifetime without compromising programming capability. The reverse conduction type doping creates a more favorable electrical environment at the gate interface.
Solution Approach 2:
The patent converts the potentially harmful effect of the p-n junction at the floating source/drain into a beneficial structure by doping it with a reverse conduction type. This transformation reduces gate leakage current and eliminates the need for high programming voltages that would otherwise be required, thereby extending device lifetime while maintaining programming functionality.
3Loss of energy
If floating source/drain is doped in reverse conduction type, then gate leakage is reduced and programming voltage can be lowered, but device structure becomes more complex
Solution Approach 1:
The patent implements local quality by applying reverse conduction type doping only to the floating source/drain region, rather than uniformly doping the entire device. This targeted approach minimizes the structural modification to only where it is most needed, reducing gate leakage current without unnecessarily complicating other device regions. The localized doping strategy balances performance improvement with structural simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and extends the lifetime of anti-fuse memory devices by reducing gate leakage and enabling efficient programming without the need for higher voltages.
Implementation Method 1
a floating source/drain doped in a reverse conduction type
Implementation Method 2
gate leakage current
Data Source
AI summary
A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.