Reverse-Conducting IGBT Pilot Diode Layout for Lower Conduction Loss
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Solution Overview
Problem
Reverse conducting insulated gate power semiconductor devices face challenges in achieving a balanced trade-off between conduction losses in diode and IGBT modes, with existing technologies experiencing high losses in both modes due to voltage snapback effects and hole injection issues.
Innovation Solution
The introduction of a pilot diode unit cell with a p-type anode region and strategically placed insulating layers to control hole injection and drainage, optimizing the layout to minimize hole drainage in IGBT mode while maintaining high hole injection in diode mode, thereby improving the conduction loss trade-off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If n-type source regions are formed in the p-type base layer to create a MOS structure, then the device achieves IGBT functionality with controlled hole injection, but voltage snapback effect occurs causing negative resistance region and increased conduction losses
Solution Approach 1:
The device is divided into separate functional regions: a first IGBT cell with MOS structure for voltage control and a second IGBT cell without MOS structure (having n-type source regions in direct contact with p-type base layer) for low-loss conduction. This segmentation allows each region to optimize for its specific function, eliminating the voltage snapback effect while maintaining IGBT functionality.
2Adaptability or versatility
If collector shorts are introduced to integrate a diode and IGBT monolithically, then the device achieves reverse conducting capability, but the voltage snapback effect is exacerbated and conduction losses increase in both modes
Solution Approach 1:
Different local structures are implemented in different cells: the first cell has the complete MOS structure with gate electrode and insulating layer for voltage control, while the second cell has n-type source regions directly contacting the p-type base layer without MOS structure. This local quality differentiation allows the second cell to operate without voltage snapback effect, reducing overall conduction losses while maintaining reverse conducting capability through the integrated diode.
3Ease of operation
If the gate electrode is used to control hole injection during diode mode, then some control over conduction is achieved, but the voltage snapback effect persists and conduction losses remain high
Solution Approach 1:
The MOS control structure (gate electrode and insulating layer) is extracted from the second IGBT cell, leaving only the n-type source regions in direct contact with the p-type base layer. This extraction eliminates the voltage snapback effect and associated conduction losses in the second cell, while the first cell retains full gate control capability for voltage management.
4Device complexity
If a single IGBT cell structure is used, then device simplicity is maintained, but it cannot simultaneously achieve low conduction losses in both IGBT and diode modes
Solution Approach 1:
The device is segmented into two distinct IGBT cells with different structures: the first cell with MOS structure for voltage control and the second cell without MOS structure for low-loss conduction. This segmentation enables the device to achieve low conduction losses in both IGBT and diode modes simultaneously, while maintaining relative structural simplicity through the use of standard semiconductor fabrication processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in significantly lower conduction losses in IGBT mode and higher hole injection in diode mode, enhancing the overall performance of reverse conducting insulated gate power semiconductor devices.
Implementation Method 1
hole injection from the base layer 142 into the drift layer 131a may be prevented
Implementation Method 2
n-type source regions 141 with a higher doping than the drift layer 131a are formed as well regions in the p-type base layer 142 at the first main side 111 of the wafer 100. An electrically insulating gate insulating layer 146 is arranged on the first main side 111 and covers part of the p-type base layer 142, the drift layer 131a and the source regions 141. The planar gate electrode 147 is formed on the gate insulating layer 146 to form a MOS structure with the gate insulating layer 146 and the base layer 142.
Implementation Method 3
The conductive channel short-circuits the pn junction between the p-type base layer 142 and the drift layer 131a. As a result, the pn junction between the p-type base layer 142 and the drift layer 131a may not be forward biased and hole injection from the base layer 142 into the drift layer 131a may be prevented. A current is maintained by the unipolar electron current flowing through the conductive channel.
Data Source
AI summary
A reverse conducting insulated gate power semiconductor device is provided which comprises a plurality of active unit cells (40) and a pilot diode unit cell (50) comprising a second conductivity type anode region (51) in direct contact with a first main electrode (21) and extending from a first main side (11) to a first depth (d1). Each active unit cell (40) comprises a first conductivity type first source layer (41a) in direct contact with the first main electrode (21), a second conductivity type base layer (42) and a first gate electrode (47a), which is separated from the first source layer (41a) and the second conductivity type base layer (42) by a first gate insulating layer (46a) to form a first field effect transistor structure. A lateral size (w) of the anode region (51) in an orthogonal projection onto a vertical plane perpendicular to the first main side (11) is equal to or less than 1 μm. On a first lateral side surface of the anode region (51) a first insulating layer (52a) is arranged and on an opposing second lateral side surface of the anode region (51) a second insulating layer (52b) is arranged. And a distance between the first insulating layer (52a) and the second insulating layer (52b) is equal to or less than 1 μm, the first insulating layer (52a) extending vertically from the first main side (11) to a second depth (d2), and the second insulating layer (52b) extending vertically from the first main side (11) to a third depth (d3), wherein the first depth (d1) is less than the second depth (d2) and less than the third depth (d3).