Reverse-Conducting IGBT Layout for Voltage Snap-Back Elimination
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Solution Overview
Problem
Reverse-conducting IGBT chips experience voltage snap-back phenomena due to the integration of IGBT and FRD, leading to increased on-resistance and high-temperature leakage currents, which affect the device's reliability and power density.
Innovation Solution
The design of a reverse-conducting IGBT chip with specific preset ranges and threshold values for short circuit regions and collector regions, optimizing the distribution of these areas to eliminate voltage snap-back phenomena and reduce parasitic PNP transistors, thereby enhancing the device's reliability and power density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If IGBT and FRD are integrated on one chip to form reverse-conducting IGBT chip, then package cost is reduced and power density is increased, but voltage snap-back phenomenon occurs leading to high on-resistance and reduced reliability
Solution Approach 1:
The patent applies local quality by creating different short circuit region density zones at different locations on the chip. The first short circuit regions are positioned in the cell region with a first density, while the second short circuit regions are positioned in the terminal region with a second density that is different from the first density. This spatial variation in short circuit region distribution allows different areas to have optimized characteristics for their specific functions, eliminating the voltage snap-back phenomenon while maintaining the integrated structure benefits.
2Reliability
If short circuit region area ratio is increased to eliminate voltage snap-back phenomenon, then device reliability is improved, but chip area is increased and power density is reduced
Solution Approach 1:
The patent optimizes chip area by implementing location-specific short circuit region densities rather than uniform distribution. The first short circuit regions in the cell region have a first density, while the second short circuit regions in the terminal region have a second density. This localized optimization ensures sufficient short circuit regions are present only where needed to eliminate the voltage snap-back phenomenon, avoiding unnecessary area consumption and maintaining high power density.
Solution Approach 2:
The patent segments the chip into distinct regions (cell region and terminal region) with different short circuit region densities. This segmentation allows each region to be optimized independently - the cell region receives short circuit regions for voltage snap-back elimination while the terminal region receives a different density appropriate for its function, thereby reducing the total chip area required compared to a uniform high-density design.
3Ease of manufacture
If uniform short circuit regions are distributed across the chip, then manufacturing is simplified, but voltage snap-back phenomenon cannot be fully eliminated
Solution Approach 1:
The patent implements local quality by specifying different densities of short circuit regions for different locations on the chip. The first short circuit regions are distributed in the cell region with a first density, while the second short circuit regions are distributed in the terminal region with a second density. This location-specific approach targets the voltage snap-back phenomenon at its source while maintaining manufacturing feasibility through systematic distribution patterns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The optimized design effectively eliminates primary and secondary voltage snap-back phenomena, reduces high-temperature leakage currents, and improves the device's reliability and power density by controlling the proportion of IGBT and FRD parts and reducing total losses in different operating modes.
Implementation Method 1
holes start to be injected from the collector region into the drift layer for forming conductivity modulation
Implementation Method 2
holes start to be injected from the collector region into the drift layer for forming conductivity modulation
Data Source
AI summary
Provided is a reverse-conducting IGBT chip including a first conductive type substrate; and several first conductive type short circuit regions arranged at intervals below the substrate and adjacent to a collector region. The short circuit regions are located outside a first preset range having the center of a chip as a center, in a second preset range outside the first preset range and having the center of the chip as a center, in a third preset range outside the second preset range and having the center of the chip as a center, and in a range outside the third preset range and enclosed by a chip edge.