Reverse Interface Logic Model for Chip Optimization
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Solution Overview
Problem
Current circuit design optimization processes face bottlenecks due to high memory and CPU requirements when simulating large composite circuits, as well as convergence issues from local optimizations that do not consider the full circuit's performance goals, leading to inefficient design throughput.
Innovation Solution
The approach involves partitioning circuits into optimization regions based on physical layout rather than logical hierarchy, using a reverse interface logic model to simplify external circuitry and create a reduced netlist that can be optimized under full circuit design constraints, allowing parallel processing and avoiding timing budget allocation issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire circuit design is simulated using a single netlist, then verification completeness is improved, but memory and CPU time requirements become excessive
Solution Approach 1:
The patent divides the full circuit design into multiple partitions based on physical layout boundaries. Each partition is simulated separately using its own netlist, reducing the computational resources required for each individual simulation while maintaining overall verification coverage through parallel processing of multiple partitions.
Solution Approach 2:
The patent introduces an interface logic model as an intermediary representation of circuit partitions. This model captures the essential timing and signal characteristics at partition boundaries, enabling accurate verification of inter-partition interactions without requiring full-chip simulation, thus reducing memory and CPU requirements.
2Productivity
If circuit design is partitioned into separate blocks for parallel processing, then processing time is reduced, but timing paths spanning multiple blocks become difficult to manage
Solution Approach 1:
The interface logic model serves as a mediator that explicitly models timing paths crossing partition boundaries. It captures delay information and signal characteristics at interfaces, enabling accurate timing analysis of multi-block paths without requiring complex manual trace-through of entire signal routes across partitions.
Solution Approach 2:
The patent implements iterative optimization where timing results from partition simulations are fed back to adjust interface logic models and partition boundaries. This feedback mechanism automatically refines the partitioning to better align with critical timing paths, simplifying timing management while maintaining parallel processing benefits.
3Speed
If local partition optimizations are performed independently, then optimization speed is improved, but convergence to global optimal performance is compromised
Solution Approach 1:
The patent merges local partition optimizations with global constraints by incorporating full-chip timing budgets and performance goals into the partition-level optimization process. Interface logic models are updated to reflect global performance requirements, ensuring that local optimizations contribute to achieving overall design targets rather than operating in isolation.
Solution Approach 2:
The optimization process uses feedback from global performance measurements to adjust partition-level constraints and interface models. Results from full-chip simulations or key metric measurements are fed back to refine partition optimizations in subsequent iterations, ensuring convergence toward global optimal performance while maintaining the speed benefits of parallel processing.
Data Source
AI summary
A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a first register occurrence. A reduced netlist spans the regional circuitry and the modeled external circuitry. Embodiments optimize the reduced netlist under design constraints applicable to the full circuit design. Changes to the original circuit design made by the optimization are tangibly saved as engineering change orders. The optimization process may be applied to other regions, including via parallel execution by multiple processors. Conventional design bottlenecks may be bypassed for greatly improved quality of results and reduced turnaround time.