Selective Reverse Mask Planarization for Interconnect Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional chemical mechanical polishing (CMP) processes struggle to achieve precise planarization of interlayer dielectric layers in semiconductor fabrication, especially for tall features, resulting in significant via height variability and imperfections.
Innovation Solution
A method involving the use of a dielectric etch stop layer and multiple distinct dielectric layers, where the etch stop layer is used to selectively remove dielectric material and control the CMP process, ensuring the top surfaces of conductive features are coplanar, and the CMP process is enhanced by a reverse mask layer to improve surface uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional CMP process is used to planarize interlayer dielectric layers, then material removal and surface smoothing are achieved, but via height variability and surface imperfections occur especially for tall features
Solution Approach 1:
The patent divides the dielectric layer into multiple segments: a first dielectric layer deposited conformally over conductive features, and a second dielectric layer deposited afterward. This segmentation allows the first layer to be selectively removed via etch-back to expose conductive features at controlled heights, while the second layer fills remaining gaps. The multi-layer approach enables precise control of via heights and reduces variability by treating different regions with different processing sequences.
Solution Approach 2:
The patent applies preliminary conformal deposition of the first dielectric layer over conductive features before subsequent processing. This preliminary action ensures uniform coverage and establishes a controlled starting point for selective removal. The etch stop layer is also deposited in advance on conductive features to control the etch-back depth, preventing over-etching and ensuring consistent via heights before the second dielectric layer is added.
2Device complexity
If single dielectric layer is deposited and planarized, then process simplicity is maintained, but surface uniformity and coplanarity of conductive features are compromised
Solution Approach 1:
The dielectric structure is segmented into a first dielectric layer and a second dielectric layer deposited at different stages. The first layer is conformally deposited and then selectively removed by etch-back, while the second layer is deposited afterward to complete the interlayer dielectric. This segmentation achieves superior surface uniformity and coplanarity of conductive features compared to a single-layer approach, as each layer can be optimized and controlled independently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces via height variability and improves surface uniformity, enabling more precise planarization of interlayer dielectric layers, even for tall features, by splitting the dielectric material deposition into multiple layers and utilizing an etch stop layer to control the CMP process.
Implementation Method 1
The CMP process combines the chemical removal effect of an acidic or basic fluid solution operating as the carrier of the slurry with the mechanical removal effect provided by an abrasive material
Implementation Method 2
The CMP process combines the chemical removal effect of an acidic or basic fluid solution operating as the carrier of the slurry with the mechanical removal effect provided by an abrasive material of the slurry that is suspended in the carrier
Implementation Method 3
selectively removing a first portion of the first dielectric layer from the top surface of at least one of the conductive features without removing a second portion of the first dielectric layer that is located between the conductive features
Data Source
AI summary
Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.