Reverse-Order RLL Coding for High-Rate Timing Recovery

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Solution Overview

Problem

Existing run-length-limited (RLL) coding techniques face challenges in maintaining efficient data transmission and storage as they require higher data throughput, leading to difficulties in clock recovery due to long runs of consecutive bits, which can result in errors and require additional error-correction mechanisms.

Innovation Solution

A high-rate RLL coding schema that adds minimal extraneous data by using a precoder, FIFO memory, histogram circuit, and XOR encoder to ensure unique decodability, limiting runs of consecutive bits and maintaining timing continuity, thereby reducing errors and improving data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional RLL coding is used to limit runs of consecutive bits, then timing recovery is improved, but data transmission rate is reduced

Engineering Contradiction:
Improvetiming recoveryVSAvoiddata transmission rate
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the fundamental parameter of run-length limitation from a strict maximum constraint to a statistical mean constraint. By controlling the expected number of consecutive bits rather than imposing a hard limit, the coding scheme achieves timing recovery while allowing longer runs that occur less frequently, thereby increasing data transmission rate.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention introduces dynamic adaptation by using feedback mechanisms to adjust coding parameters based on the actual run-length statistics observed in the data stream. This allows the system to optimize between timing recovery requirements and transmission rate by dynamically modifying the coding strategy.

Inventive Principle:
Principle #15Dynamics

2Productivity

If higher data throughput is achieved, then productivity is improved, but error susceptibility increases due to longer runs of consecutive bits

Engineering Contradiction:
Improvedata throughputVSAvoiderror susceptibility
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements feedback mechanisms that monitor the actual run-length distribution in the encoded data stream and adjust coding parameters accordingly. This feedback loop ensures that even at high data throughput rates, the statistical properties of the code maintain acceptable error susceptibility by preventing excessive consecutive bits.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

By transitioning from fixed run-length limits to dynamically adjusted statistical parameters, the system can achieve higher throughput while maintaining reliability through continuous parameter optimization based on observed performance.

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If strict run-length constraints are imposed, then timing continuity is maintained, but coding efficiency is reduced

Engineering Contradiction:
Improvetiming continuityVSAvoidcoding efficiency
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

Instead of imposing strict run-length constraints on all bit sequences, the patent applies partial control by managing the statistical distribution of run-lengths. This allows most sequences to be more flexible while maintaining sufficient timing continuity through controlled averaging, thereby improving coding efficiency.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The invention changes the constraint parameter from a strict maximum run-length value to a statistical mean run-length value, allowing greater flexibility in individual sequences while maintaining overall timing continuity through statistical control.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9136869B2High-rate reverse-order run-length-limited code
Publication Date: 2015.09.15 STMICROELECTRONICS INT NV
  • US9136869B2 patent drawing
  • US9136869B2 patent drawing
  • US9136869B2 patent drawing

AI summary

A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.