Reverse SOI Wafer Structure With SiGe Etch Stop and TSV
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Solution Overview
Problem
Existing methods for producing silicon-on-insulator (SOI) wafers face challenges in achieving high yield with defect-free device layers and uniform thickness while maintaining cost-effectiveness.
Innovation Solution
A semiconductor structure with a reverse SOI configuration and through-silicon via (TSV) is fabricated using a silicon epitaxial tri-layer, including an etch selectivity layer of SiGe, which allows for precise thickness control and defect-free device layers through selective grinding and etching, followed by bonding and TSV formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to produce SOI wafers, then manufacturing cost is reduced, but yield and defect-free device layers deteriorate
Solution Approach 1:
The substrate is divided into multiple layers with distinct functions: a sacrificial first substrate, an etch stop layer, and a device layer. This segmentation allows selective removal of the first substrate while preserving the device layer, achieving both cost-effectiveness and high yield through controlled material removal and precise layer differentiation.
Solution Approach 2:
The etch stop layer acts as an intermediary between the sacrificial first substrate and the device layer. It enables selective etching by providing a controlled interface that stops the etching process at the desired depth, ensuring defect-free device layers while maintaining manufacturing efficiency.
2Device complexity
If conventional methods are used to produce SOI wafers, then manufacturing simplicity is maintained, but thickness uniformity and defect-free layers deteriorate
Solution Approach 1:
The etch stop layer is formed in advance with controlled thickness and uniformity before device layer fabrication. This preliminary action establishes a precise reference plane that guides subsequent processing steps, ensuring consistent thickness uniformity across the wafer while maintaining overall process simplicity.
Solution Approach 2:
The patent replaces complex mechanical thickness control methods with a chemically-based etch stop mechanism. The etch stop layer provides a self-limiting etching endpoint that automatically ensures uniform thickness without requiring complex mechanical positioning or control systems.
3Manufacturing precision
If selective grinding and etching are used with SiGe etch stop layer, then thickness variation is reduced and defect-free layers are achieved, but device complexity and process steps increase
Solution Approach 1:
The patent changes the material composition parameter by introducing a SiGe etch stop layer with different etch selectivity compared to silicon. This parameter change enables selective removal of the first substrate while preserving the device layer, achieving superior thickness uniformity and defect-free layers through material property differentiation rather than increased process complexity.
4Productivity
If high-yield methods are used to produce SOI wafers, then productivity is improved, but thickness variation and defects increase
Solution Approach 1:
The etch stop layer serves as a mediator that decouples the conflict between high-yield production and thickness uniformity. It provides a controlled etching endpoint that ensures consistent device layer thickness across all wafers, enabling high-yield manufacturing without sacrificing precision or introducing defects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves high-yield, defect-free SOI wafers with reduced thickness variation and cost-effective manufacturing by utilizing SiGe as an etch stop layer for precise substrate removal and TSV integration.
Implementation Method 1
selective grinding and etching
Implementation Method 2
silicon epitaxial tri-layer
Implementation Method 3
bonding
Data Source
AI summary
The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the first surface is at a front side of the semiconductor device layer, and the second surface is at a backside of the semiconductor device layer; an insulating layer above the second surface of the semiconductor device; and a through-silicon via (TSV) traversing the insulating layer. Associated manufacturing methods of the same are also provided.