Reverse Spacer for Gate Length Control in CMOS Transistors
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Solution Overview
Problem
The fabrication of advanced integrated circuits using CMOS technology faces challenges in reducing transistor channel length while maintaining capacitive coupling and avoiding leakage currents, particularly with the use of ultra-thin silicon dioxide gate insulation layers, which can lead to increased complexity and variability in transistor performance due to the need for precise patterning and deposition of high-k dielectric materials.
Innovation Solution
The introduction of a reverse spacer with a tapered cross-sectional shape within the gate opening, formed on the inner sidewalls before filling with metal species, reduces the criticality of the deposition process and allows for more precise control of gate length without increasing process complexity, enhancing the integrity of sensitive materials and reducing deposition-related irregularities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel length is decreased to improve switching speed and drive current capability, then transistor performance is improved, but the thickness of the silicon dioxide gate insulation layer must be correspondingly reduced, leading to increased leakage current due to direct tunneling
Solution Approach 1:
The patent changes the material parameter of the gate insulation layer from conventional silicon dioxide to high-k dielectric materials (such as hafnium oxide, tantalum oxide, or strontium titanium oxide). These materials have significantly higher permittivity, allowing the gate insulation layer to be physically thicker while maintaining the same capacitive coupling, thereby reducing leakage current through direct tunneling while preserving switching speed performance
2Reliability
If the thickness of the silicon dioxide gate insulation layer is reduced to maintain capacitive coupling in short channel transistors, then capacitive coupling is maintained, but leakage current increases exponentially
Solution Approach 1:
The patent changes the permittivity parameter of the gate insulation layer by using high-k dielectric materials. This allows the physical thickness to be increased while maintaining the same capacitance per unit area (C = kε0A/d), thereby reducing the exponential leakage current associated with ultra-thin silicon dioxide while preserving the necessary capacitive coupling for reliable transistor operation
3Manufacturing precision
If physical vapor deposition techniques are used to deposit metal species in gate openings, then deposition directionality is improved, but deposition-related irregularities and overhangs increase, particularly in reduced dimensions
Solution Approach 1:
The patent performs preliminary actions by forming spacer structures on the inner sidewalls of gate openings before depositing metal species. These spacers prepare the gate opening geometry by creating a tapered cross-sectional shape that facilitates more uniform metal deposition, reducing overhangs and deposition irregularities while maintaining the directionality benefits of physical vapor deposition techniques
Solution Approach 2:
The patent addresses the deposition problem by transitioning from a two-dimensional planar gate opening to a three-dimensional tapered structure with spacers on the inner sidewalls. This dimensional change in the gate opening geometry allows metal species to deposit more uniformly throughout the opening, reducing the overhangs and irregularities that occur in straight-walled openings
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient reduction of gate length and minimizes transistor variability, maintaining high yield and reliability by providing a superior cross-sectional shape that reduces the influence of overhangs and deposition irregularities, thus addressing the challenges of short channel behavior and leakage currents.
Implementation Method 1
The introduction of a reverse spacer with a tapered cross-sectional shape within the gate opening, formed on the inner sidewalls before filling with metal species
Data Source
AI summary
In a replacement gate approach, a spacer may be formed in the gate opening after the removal of the placeholder material, thereby providing a superior cross-sectional shape upon forming any electrode metals in the gate opening. Moreover, the spacer may be used for reducing the gate length, while not requiring more complex gate patterning strategies.