Reverse T-Shape Gate Dielectric for Semiconductor Fabrication
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Solution Overview
Problem
In the semiconductor industry, the conventional polysilicon gate electrodes face issues such as boron penetration and depletion, leading to inferior performance, and during the fabrication of high-k metal transistors, over-etching and undercut problems occur, causing erosion in the high-k dielectric layer and bottom barrier metal, which affects device performance.
Innovation Solution
A method is developed to fabricate a semiconductor device with a gate dielectric layer having a reverse T-shape, where a gate electrode is formed with a top surface of the gate dielectric layer adjacent to the sides being lower than between the gate electrode and the substrate, and spacers are created using mask layers to prevent over-etching and maintain the integrity of the high-k dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional polysilicon gate is used, then fabrication process is simple, but device performance deteriorates due to boron penetration and depletion effect
Solution Approach 1:
The patent changes the material parameter of the gate electrode from conventional polysilicon to metal materials (such as tungsten, cobalt, or copper), fundamentally altering the electrical and chemical properties to eliminate boron penetration and depletion effects while maintaining fabrication feasibility through established metal deposition techniques
Solution Approach 2:
The patent employs a composite gate structure consisting of multiple layers including metal gate electrode, high-k dielectric layer, and barrier metal layer, where each material serves a specific function: the metal provides high conductivity, the high-k dielectric provides superior insulation, and the barrier metal prevents diffusion, creating a synergistic composite structure that overcomes the limitations of single-material polysilicon gates
2Ease of operation
If over-etching is performed during spacer formation, then spacer coverage is improved, but erosion occurs in high-k dielectric layer and bottom barrier metal
Solution Approach 1:
The patent introduces a protective capping layer (such as silicon nitride or silicon oxynitride) over the high-k dielectric layer and bottom barrier metal before the etching process. This preliminary protective action creates a physical barrier that prevents etching gas from reaching and eroding the sensitive layers, allowing the etching process to proceed with adequate coverage without compromising structural integrity
Solution Approach 2:
The protective capping layer serves as an intermediary element between the etching environment and the sensitive high-k dielectric layer. It absorbs the harmful effects of over-etching and undercut, transferring the etching damage to itself rather than to the critical dielectric and barrier metal layers, thereby enabling process flexibility while maintaining precision
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of first forming a gate dielectric layer on a substrate; forming a gate material layer on the gate dielectric layer, and removing part of the gate material layer and part of the gate dielectric layer to form a gate electrode, in which a top surface of the gate dielectric layer adjacent to two sides of the gate electrode is lower than a top surface of the gate dielectric layer between the gate electrode and the substrate. Next, a first mask layer is formed on the gate dielectric layer and the gate electrode, part of the first mask layer and part of the gate dielectric layer are removed to form a first spacer, a second mask layer is formed on the substrate and the gate electrode, and part of the second mask layer is removed to forma second spacer.