Reverse Taper Contact Plug for Dual Stress Liner Etching
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Solution Overview
Problem
The dual-stress liner technology for n-type and p-type field-effect transistors (FETs) faces challenges in achieving uniform etching of contact holes due to uneven liner thickness, leading to under-etching or over-etching issues, which result in increased contact resistance and reduced performance.
Innovation Solution
Forming conductive plugs with reverse taper sidewalls, having a bottom inner taper angle of less than 90 degrees, to ensure proper contact with the silicon layer and reduce resistance, and using a barrier layer to prevent material migration, while avoiding the conventional problems of under-etching and over-etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional tapered plugs with bottom inner taper angle greater than 90 degrees are used, then the etching process is simpler, but the contact area between plug and silicon layer is reduced, increasing contact resistance
Solution Approach 1:
The patent inverts the conventional plug taper geometry. Instead of having sides taper inward from top to bottom (creating a smaller bottom area), the plug sides taper outward from top to bottom, creating a larger bottom contact area. This reverse taper configuration directly addresses the contact resistance issue by maximizing the contact area between the plug and silicon layer while still being compatible with standard etching processes
2Reliability
If dual-stress liner technology is used to improve FET performance, then transistor performance is enhanced, but the uneven liner thickness causes under-etching or over-etching in contact holes
Solution Approach 1:
The patent applies different liner thickness configurations in different regions of the semiconductor device. In regions where contact holes are formed, the liner thickness is specifically controlled to enable proper etching. The reverse taper plug design works in conjunction with localized liner thickness adjustments to ensure that contact holes etch uniformly across both overlap and non-overlap regions, while still maintaining the dual-stress liner benefits for FET performance in other areas
3Reliability
If the liner thickness is doubled in overlap regions to prevent moisture entry, then device protection is improved, but contact hole etching becomes non-uniform across the wafer
Solution Approach 1:
The patent changes the geometric parameters of the contact structure to compensate for the doubled liner thickness in overlap regions. By using reverse taper plugs with specific dimensional relationships, the etching process can penetrate through the thicker liner uniformly. The parameter changes in plug geometry allow the etch to reach the silicon layer consistently, maintaining productivity and uniformity despite the increased liner thickness required for device protection
Data Source
AI summary
A semiconductor device having a silicon layer, a transistor having an electrical connection region in the silicon layer; and a conductive plug formed on and in electrical contact with the electrical connection region, the plug having side walls that taper inward away from the silicon layer.