Reverse TLB Lookup for Heterogeneous Multi-Core Coherency
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Solution Overview
Problem
Current methods for maintaining coherency in multi-core heterogeneous computing systems, particularly those with different processor architectures, are inefficient due to reliance on virtual address schemes and sequential TLB entry examination, leading to high processing time and power consumption.
Innovation Solution
Implementing a reverse translation lookaside buffer (TLB) look-up method using physical addresses, which allows for efficient identification and flushing of TLB entries by generating and comparing values from masks and page frame numbers, enabling batch invalidation and promoting coherency without serial operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional virtual address-based TLB look-up methods are used in heterogeneous multi-core systems, then TLB coherency can be maintained, but processing time and power consumption increase significantly
Solution Approach 1:
The patent inverts the conventional TLB look-up approach by using physical addresses instead of virtual addresses to identify and invalidate TLB entries. Instead of translating virtual addresses to physical addresses and then searching for matching entries, the system directly uses physical addresses to probe the TLB, reversing the traditional lookup direction and enabling faster coherency maintenance in heterogeneous systems
Solution Approach 2:
The patent changes the key parameter used for TLB entry identification from virtual addresses to physical addresses. This parameter change allows the system to bypass virtual-to-physical translation overhead and directly match physical addresses against TLB entries, significantly reducing processing time while maintaining coherency across heterogeneous processor architectures
2Reliability
If sequential examination of TLB entries is performed to maintain coherency, then all entries can be checked for matches, but power consumption and processing time increase
Solution Approach 1:
The patent extracts the essential identifying feature from TLB entries (the physical address portion) and uses it directly for matching purposes. By extracting and utilizing only the necessary physical address components rather than examining entire virtual address translations, the system reduces the search space and enables faster, more energy-efficient coherency checks
Solution Approach 2:
The patent applies partial action by using only the necessary physical address portions for TLB entry matching rather than performing complete virtual address translations and full entry examinations. This selective approach checks only the critical physical address bits needed for identification, reducing both processing time and power consumption while maintaining coherency
3Productivity
If many-to-one mapping of virtual pages to physical pages is used in TLBs, then memory access efficiency is improved, but coherent identification of entries becomes expensive
Solution Approach 1:
The patent inverts the identification approach by using physical addresses to directly probe TLB entries rather than translating virtual addresses and searching for matches. This reversal exploits the many-to-one mapping structure by allowing multiple virtual addresses that map to the same physical address to be efficiently identified through a single physical address probe, reducing identification time while maintaining memory access efficiency
Data Source
AI summary
Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match.