Hardware Reverse Translation Unit for Memory Error Management

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Solution Overview

Problem

Existing computer systems face challenges in managing memory errors in physical memory modules, particularly with DIMMs, which can be unreliable and require complex software solutions for address translation across varying memory schemes, leading to high development and validation costs.

Innovation Solution

A hardware translation unit is implemented to translate target module addresses into System Physical Address (SPA) addresses, enabling reverse translation without the need for separate software translators, thus simplifying the process and reducing costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If software translators are used for address translation, then reverse translation capability is achieved, but development and validation costs increase significantly

Engineering Contradiction:

Improvememory error management reliabilityVSAvoiddevelopment and validation cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces software-based address translation mechanisms with hardware-based translation units (reverse translation unit 136, translation unit 140) integrated into the memory controller. This substitution eliminates the need for complex software translators, reducing development and validation costs while maintaining reliable reverse translation capability for memory error management.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Adaptability or versatility

If separate software translators are implemented, then address translation functionality is provided, but system complexity increases

Engineering Contradiction:

Improveaddress translation capabilityVSAvoidsystem complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges the translation functionality into the memory controller hardware by integrating reverse translation unit 136 and translation unit 140 directly into the memory control logic. This consolidation eliminates separate software translator components, reducing system complexity while maintaining full address translation and reverse translation capabilities through unified hardware structures.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11307996B2Hardware unit for reverse translation in a processor

Publication Date: 2022.04.19 INTEL CORP

AI summary

In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.