Reverse Wire Bonding for CSP Package Loop Stability
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Solution Overview
Problem
In semiconductor manufacturing, particularly for CSP devices, the narrow distance between the semiconductor chip and the wiring substrate leads to wire connection failures due to insufficient wire feeding and friction issues during the bonding process, especially when using the forward bonding system, resulting in shorting and instability of the wire loop.
Innovation Solution
The implementation of a reverse bonding system where the wire is disposed on a side closer to the periphery than the wire connecting portion at the terminal of the wiring substrate, allowing for a longer wire length and stable loop formation by detouring the wire outside the connecting portion, thus synchronizing the wire feed rate with the capillary movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If forward bonding system is used with narrow distance between chip and wiring substrate, then bonding process can be performed, but wire may fail to enter between capillary and chip end causing connection failure
Solution Approach 1:
The patent inverts the bonding sequence by performing reverse bonding instead of forward bonding. The capillary first bonds to the chip electrode, then pulls the wire outward to form a loop, and finally bonds to the wiring substrate terminal. This inversion allows the wire to be pulled outward rather than pushed inward, ensuring proper wire entry and loop formation even in narrow spaces of CSP packages.
2Reliability
If capillary is extended to prevent wire interference, then wire entry is improved, but capillary bends at narrow portion disturbing ultrasonic wave conduction
Solution Approach 1:
By inverting the bonding sequence, the capillary maintains a more favorable structural configuration throughout the process. The capillary bonds to the chip first, then pulls the wire outward in a controlled manner, avoiding the need for excessive capillary extension that would cause bending and ultrasonic wave disruption.
3Reliability
If reverse bonding system is used, then wire connection failure is prevented, but wire length becomes too small causing contact with chip end
Solution Approach 1:
The patent employs dynamic control of the capillary movement and wire feeding throughout the bonding process. The capillary elevates and moves horizontally in a coordinated sequence, while the wire is fed at controlled rates to maintain appropriate tension and length. This dynamic coordination ensures the wire is long enough to form a stable loop without contacting the chip end, resolving the contradiction between connection reliability and wire length.
4Stability of the object's composition
If wire feed rate is increased to match capillary movement, then loop stability is improved, but friction between capillary and wire increases causing wear
Solution Approach 1:
The inverted bonding sequence changes the relative motion dynamics between the capillary and wire. By bonding to the chip first and then pulling the wire outward, the wire moves more smoothly through the bonding zone with reduced friction and contact pressure, decreasing capillary wear while maintaining loop stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces shorting between the terminal and the chip, prevents wire connection failures, and stabilizes the wire loop shape, enhancing the reliability of the bonding process even in small package sizes.
Implementation Method 1
connecting a tip portion of a wire to a terminal of the wiring substrate, moving a capillary to a direction distant from the semiconductor chip to pull the wire from the terminal, disposing the capillary on the electrode of the semiconductor chip
Implementation Method 2
A nail head bonding system using ultrasonic wave in combination is employed in wire bonding
Data Source
AI summary
A semiconductor device including a package substrate having, at the periphery of the main surface thereof, bonding leads disposed in a row, a semiconductor chip mounted inside of the row of the bonding leads on the main surface of the package substrate, wires for connecting pads of the semiconductor chip and the bonding leads of the substrate, a sealing body for resin sealing the semiconductor chip and the wires, and solder bumps disposed on the back surface of the package substrate. The top of a loop of each of the wires is disposed outside the wire connecting portion so that the wire connection between the bonding leads and the pads of the semiconductor chip has a stable loop shape to prevent wire connection failure.