Reversed-Profile Copper Pillar Packaging for High-Density I/O
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Solution Overview
Problem
As semiconductor chips become smaller and more functional, integrating a greater number of I/O pads into smaller areas complicates packaging, leading to yield issues due to increased difficulty in redistributing connections effectively.
Innovation Solution
The development of a packaging process involving a copper pillar with a reversed profile, where a polymer layer is formed over metal pads, baked to reflow and reduce sidewall tilt angles, and metal pillars are formed with specific profiles to enhance contact and reduce stress, allowing for efficient redistribution lines and encapsulation to connect I/O pads without increasing die area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of I/O pads is increased to integrate more functions, then the functionality of semiconductor chips is improved, but the packaging difficulty increases and yield decreases
Solution Approach 1:
The patent transitions from planar 2D pad layout to 3D vertical interconnection structures with copper pillars extending through multiple dielectric layers, enabling I/O pads to be distributed across different elevation levels and thereby increasing packaging capacity without proportionally increasing die area
Solution Approach 2:
The patent implements nested structures where copper pillars are embedded within dielectric layers, which are in turn surrounded by additional dielectric layers and metal interconnects, creating multi-layer nested configurations that maximize space utilization for high-density I/O packaging
2Area of stationary object
If I/O pads are packed into smaller areas to reduce die size, then the die area is reduced, but the density of I/O pads increases making packaging more difficult
Solution Approach 1:
The patent utilizes vertical dimension by forming copper pillars that extend through multiple dielectric layers at different heights, allowing I/O pads to be arranged in three-dimensional space rather than confined to a single plane, thus achieving high density without excessive planar compression
Solution Approach 2:
The patent divides the interconnection structure into segmented layers with dielectric layers separated by metal interconnect layers containing copper pillars, allowing independent optimization of each layer's pad density and facilitating precise manufacturing control for high-density packaging
3Ease of manufacture
If copper pillars are formed with standard profiles, then the manufacturing process is simple, but stress and delamination occur during packaging
Solution Approach 1:
The patent employs asymmetric copper pillar profiles where the sidewall angles differ between upper and lower portions, with the lower portion having a larger tilt angle than the upper portion, creating an optimized stress distribution pattern that reduces delamination risk while maintaining manufacturing feasibility
Solution Approach 2:
The patent applies different geometric characteristics to different regions of the copper pillar structure, with the lower portion featuring larger tilt angles for stress reduction and the upper portion featuring smaller tilt angles for connection stability, thereby optimizing local properties to address specific functional requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process improves packaging efficiency by reducing stress and delamination, enabling reliable electrical connections and increased I/O pad density without area expansion, thus addressing the yield challenges in semiconductor packaging.
Implementation Method 1
a polymer layer is formed over metal pads, baked to reflow and reduce sidewall tilt angles
Data Source
AI summary
A method includes forming a first polymer layer to cover a metal pad of a wafer, and patterning the first polymer layer to form a first opening. A first sidewall of the first polymer layer exposed to the first opening has a first tilt angle where the first sidewall is in contact with the metal pad. The method further includes forming a metal pillar in the first opening, sawing the wafer to generate a device die, encapsulating the device die in an encapsulating material, performing a planarization to reveal the metal pillar, forming a second polymer layer over the encapsulating material and the device die, and patterning the second polymer layer to form a second opening. The metal pillar is exposed through the second opening. A second sidewall of the second polymer layer exposed to the second opening has a second tilt angle greater than the first tilt angle.