Reversed Switching in Split-Capacitor SAR ADCs for Linearity
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Solution Overview
Problem
Successive approximation register (SAR) analog-to-digital converters (ADCs) suffer from nonlinear errors due to capacitance mismatch in capacitor arrays, leading to reduced accuracy and linearity in analog-to-digital conversion.
Innovation Solution
A 3-bit split-capacitor SAR ADC design that employs two capacitor arrays and selection circuits, along with a comparator and control logic circuit, to sample and compare differential input voltages, using reference voltages to reduce voltage errors and mismatch-induced nonlinearity errors through a method of capacitor switching and voltage resetting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If capacitor arrays are used in SAR ADC for low power consumption, then power efficiency is improved, but capacitance mismatch occurs leading to nonlinear errors and reduced accuracy
Solution Approach 1:
The single capacitor array is divided into two separate capacitor arrays (first capacitor array and second capacitor array). Each array independently processes one polarity of the differential input signal, eliminating the capacitance mismatch problem that occurs in single-array designs while maintaining low power consumption characteristics of SAR ADC.
Solution Approach 2:
Different capacitor arrays are assigned to different polarities of the input signal (positive and negative). This local specialization allows each capacitor array to be optimized for its specific function, reducing the impact of capacitance mismatch on overall conversion accuracy while maintaining energy efficiency.
2Device complexity
If capacitor arrays are used in SAR ADC, then the converter structure is simplified, but capacitance mismatch leads to integral and differential nonlinearity errors
Solution Approach 1:
The capacitor array is segmented into multiple independent arrays, each handling specific signal polarities. This segmentation reduces the capacitance mismatch within each individual array while maintaining overall structural simplicity through modular design and systematic switching control.
Solution Approach 2:
Instead of trying to achieve perfect matching in a single capacitor array, the design inverts the approach by using multiple arrays with intentional asymmetry in their connection configurations. The switching circuitry compensates for the apparent complexity by providing systematic control that actually simplifies the overall design while improving linearity.
3Speed
If conventional capacitor switching is used in SAR ADC, then conversion speed is maintained, but nonlinear errors reduce conversion accuracy
Solution Approach 1:
The switching circuitry is designed to dynamically select and connect appropriate capacitor arrays based on the polarity of the input signal. This dynamic configuration maintains fast conversion speed by avoiding complex sequential operations while improving accuracy through intelligent real-time adaptation to signal conditions.
Solution Approach 2:
The system changes the operational parameters (which capacitor array is active, which switches are closed) based on the input signal characteristics. This parameter adaptation allows the converter to maintain high speed operation while dynamically optimizing for accuracy by selecting the appropriate capacitor array configuration for each conversion cycle.
Data Source
AI summary
A method of operating an analog-to-digital converter includes in a first conversion period, a comparator generating a first comparison result, a first selection circuit switching a voltage output to a first capacitor of a set of larger capacitor of a first capacitor array, and a second selection circuit switching a voltage output to a second capacitor of a set of larger capacitor of a second capacitor array, and in a second conversion period after the first conversion period, the comparator generating a second comparison result different from the first comparison result, the first selection circuit switching back the voltage output to a first capacitor portion of the first capacitor of the set of larger capacitor of the first capacitor array, and the second selection circuit switching back the voltage output to a first capacitor portion of the second capacitor of the set of larger capacitor of the second capacitor array.