Reversible Polarity Decoder Circuit for 3D Memory Arrays
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Solution Overview
Problem
In semiconductor memory arrays, especially in 3D technology, the high voltages required for programming and erasing passive element memory cells exceed the breakdown voltages of high-voltage transistors, making it difficult to achieve the necessary voltage swing in decoder circuits without breakdown, particularly as the array line pitches decrease, and dual polarity outputs are needed for row and column decoders.
Innovation Solution
A decoder circuit design that includes multiple bias nodes and coupling circuits to manage voltage across decoder output driver circuits, limiting the voltage across individual devices to prevent breakdown, and utilizing transfer gate circuits to achieve the required voltage swing for both selected and unselected modes of operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high voltage transistors are used to achieve the required voltage swing for programming and erasing memory cells, then the voltage requirement is met, but the transistor breakdown voltage is exceeded and the transistors do not scale well with decreasing memory cell pitch
Solution Approach 1:
The decoder output driver circuit is segmented into multiple coupling circuits (first coupling circuit, second coupling circuit, third coupling circuit) that divide the voltage swing path. Each coupling circuit contains transistors that operate within their breakdown voltage limits, while collectively achieving the required high voltage swing across the memory cell through series connection.
Solution Approach 2:
Multiple intermediate bias nodes (first bias node, second bias node, third bias node) are introduced as mediators to distribute and control the voltage across different coupling circuits. These intermediate nodes enable the system to achieve high voltage swing without any single transistor experiencing breakdown conditions.
2Ease of operation
If the voltage swing of row decoder outputs is increased to provide even higher voltage bias to half-selected word line driver circuits, then half-selected word lines are maintained at inactive level, but transmission gate circuits break down when operated at voltage swing larger than array drivers
Solution Approach 1:
The voltage biasing path to half-selected word line drivers is segmented into multiple coupling circuits with intermediate bias nodes. This segmentation allows the system to provide high voltage bias to half-selected word lines while keeping individual transistor voltages within safe operating limits.
Solution Approach 2:
Different coupling circuits are configured with different voltage ratings and configurations appropriate to their specific function. The first coupling circuit handles the selected word line voltage, while the second and third coupling circuits handle the half-selected word line biasing, each optimized for their local voltage requirements.
3Adaptability or versatility
If dual polarity outputs are implemented in row and column decoders for programming and erasing modes, then both programming and erasing operations are enabled, but achieving required voltage swing for both polarities becomes difficult without encountering breakdown problems
Solution Approach 1:
The decoder output driver circuit is designed as a universal multi-functional circuit that can operate in both programming mode (forward polarity) and erasing mode (reverse polarity). The same coupling circuits and bias nodes serve both polarities, achieving dual functionality without requiring separate dedicated circuits for each mode.
Solution Approach 2:
The circuit dynamically adapts its configuration based on the operating mode. Bias signals are dynamically adjusted to provide appropriate voltage levels for either programming or erasing operations, allowing the circuit to flexibly handle both polarities while maintaining transistor safety margins.
Data Source
AI summary
A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.