Reversible Logic Address Decoder Self-Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Address decoders in memories are timing-critical and prone to marginal defects due to manufacturing issues or aging, particularly Bias Temperature Instability (BTI), which can lead to timing violations and operation failures, necessitating improved testing methods to identify timing violations reliably.
Innovation Solution
Implementing conservative reversible logic in address decoders allows for 100% transition fault coverage through self-testing by applying logic state vectors and verifying correct propagation delays, enabling full testing of the decoder with a single memory address write operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional address decoder testing is performed with multiple test patterns, then timing violations can be detected, but chip area increases and execution time increases
Solution Approach 1:
The address decoder is designed to perform both normal decoding operations and self-testing functions using the same hardware resources. By utilizing the decoder's inherent reversible and conservative logic properties, the system can test all address lines and detect timing violations without requiring separate dedicated test pattern storage circuits, thereby eliminating the need for additional chip area.
Solution Approach 2:
The address decoder performs self-testing by automatically detecting its own timing violations through its inherent reversible logic structure. The decoder monitors its own operation during normal functioning, eliminating the need for external test equipment or additional test circuitry, thus avoiding any increase in chip area while maintaining high reliability.
2Reliability
If traditional address decoder testing is performed with multiple test patterns, then timing violations can be detected, but execution time increases
Solution Approach 1:
The self-testing mechanism operates continuously during normal decoder operation without requiring separate test execution phases. The reversible and conservative logic structure enables the decoder to monitor its own timing performance in real-time, eliminating the need to halt application execution for dedicated test periods, thus reducing time loss while maintaining detection reliability.
Solution Approach 2:
The address decoder simultaneously performs normal addressing functions and self-diagnosis of timing violations. This multi-functionality allows the system to detect timing issues during regular operation without requiring separate test execution time, thereby maintaining high reliability while minimizing execution time overhead.
3Reliability
If conservative reversible logic is used in address decoder, then 100% transition fault coverage is achieved, but device complexity increases
Solution Approach 1:
The address decoder utilizes conservative reversible logic gates (such as Fredkin gates) that maintain a constant number of logic high signals through their operation. This parameter conservation property enables complete transition fault coverage by ensuring that all possible signal transitions are observable, while the systematic structure of these gates keeps the complexity increase manageable compared to traditional irreversible logic designs.
Solution Approach 2:
The conservative reversible logic structure creates a bijective mapping between input and output states, effectively creating a copy of the input state at the output. This property enables complete fault coverage by allowing observation of all transition patterns, while the regular and systematic nature of the logic gate implementation keeps the overall device complexity controlled.
Data Source
AI summary
An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.