Reversible Leadless Package for High-Density Semiconductor Stacking
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Solution Overview
Problem
Current semiconductor device packages face challenges in minimizing profile height while increasing die density and reducing electrical path length, particularly due to complexity in assembly and thermal management issues when stacking dies, which often results in unsalvageable packages if defects occur.
Innovation Solution
A semiconductor device package design featuring a molding compound covering a semiconductor device and an electrically conductive lead frame with posts and post extensions, allowing for wire bonding or flip-chip connections, and enabling the package to be assembled using standard QFN equipment, with the option to stack packages for increased density without an insulative layer, and be mounted in either orientation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If dies are stacked inside a single package to increase die density and decrease electrical path length, then die density increases and electrical path length decreases, but assembly complexity increases and thermal management becomes difficult
Solution Approach 1:
The invention divides the system into multiple independent packages rather than stacking dies within a single package. Each package contains one die and can be assembled independently using standard QFN equipment, eliminating the complexity of multi-die assembly while achieving high density through parallel packaging
Solution Approach 2:
The invention transitions from vertical stacking (z-dimension) to horizontal arrangement (x-y plane) of multiple packages. Contact surfaces are provided on both top and bottom faces of each package, enabling flexible spatial arrangement and high-density integration without increasing assembly complexity
2Quantity of substance
If dies are stacked inside a single package, then die density increases, but the package thickness increases creating thermal management issues
Solution Approach 1:
By separating dies into individual packages rather than stacking them, each package maintains a thin profile with excellent thermal characteristics. Heat dissipation paths are shortened and direct, avoiding the thermal accumulation problems inherent in stacked configurations
Solution Approach 2:
The invention achieves high die density through horizontal arrangement of multiple thin packages rather than vertical stacking. This dimensional transition maintains thin package profiles while accommodating multiple dies, thereby preserving thermal management performance
3Reliability
If wirebonding is used to electrically connect stacked dies, then electrical connections are established, but the top die must be smaller than the bottom die to allow sufficient peripheral space
Solution Approach 1:
Each die is packaged independently without requiring wirebond connections to other dies. The electrical connections are made directly from each die to external circuitry through the lead frame, eliminating the need for hierarchical die stacking and associated size constraints
Solution Approach 2:
The invention extracts the wirebonding inter-die connection requirement by providing direct external connections for each die. This eliminates the peripheral space constraints that would otherwise be necessary to accommodate wirebonding infrastructure
4Reliability
If a package with stacked dies is assembled and defects occur, then the entire package including all chips becomes unsalvageable, but individual package testing and replacement is enabled with separate packages
Solution Approach 1:
By packaging each die separately rather than stacking multiple dies in one package, the system achieves modular fault isolation. If one package fails, only that single package needs to be replaced rather than the entire multi-die assembly, thereby reducing waste and improving reliability
Solution Approach 2:
The invention enables selective replacement of defective individual packages while retaining functional packages. This minimizes waste by recovering and reusing non-defective packages, rather than discarding entire stacked assemblies when a single die fails
Data Source
AI summary
A semiconductor device package includes an electrically conductive lead frame having a plurality of posts disposed at a perimeter of the package. Each of the posts has a first contact surface disposed at the first package face and a second contact surface disposed at the second package face. The lead frame also includes a plurality of post extensions disposed at the second package face. Each of the post extensions includes a bond site formed on a surface of the post extension opposite the second package face. At least one I/O pad on the semiconductor device is electrically connected to the post extension at the bond site using wirebonding, tape automated bonding, or flip-chip methods. The package can be assembled using a lead frame having pre-formed leads, with or without taping, or using partially etched lead frames. A stack of the semiconductor device packages may be formed.