Reversible Polarity Decoder Circuit for 3D Memory Arrays
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Solution Overview
Problem
Existing decoder circuits for passive element memory arrays face challenges in achieving high voltage swings across memory cells without encountering breakdown issues, especially when operating at the breakdown voltage of transistors, particularly in 3D memory technology where high voltage transistors do not scale well with decreasing array line pitches.
Innovation Solution
The proposed decoder circuit employs a dual polarity row decoder with a multi-headed structure that includes a decoded source selection bus and a decoded reverse source selection bus, allowing for flexible voltage biasing of half-selected word lines and bit lines, and utilizes a split voltage technique to reduce voltage requirements, thereby preventing transistor breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stress or pressure
If high voltage transistors are used to achieve high voltage swings across memory cells, then the voltage requirement is met, but the transistor breakdown voltage is exceeded and scaling is compromised
Solution Approach 1:
The decoder circuit is divided into multiple stages: a first decoder stage operating at low voltage to generate intermediate decoded signals, and a second decoder stage that conditionally inverts these signals based on polarity control. This segmentation allows the circuit to achieve high voltage swings at the output without subjecting internal transistors to breakdown voltages, as each stage operates within safe voltage limits.
Solution Approach 2:
A polarity control mechanism acts as an intermediary between the first and second decoder stages. This intermediary conditionally inverts decoded signals based on polarity control signals, enabling the circuit to switch between active-high and active-low output modes without requiring the transistors to withstand extreme voltage swings, thus preventing breakdown while maintaining reliability.
2Adaptability or versatility
If dual polarity outputs are implemented to support forward set/reverse reset operations, then operational versatility is improved, but circuit complexity increases
Solution Approach 1:
The decoder circuit is designed with multi-functionality to handle both forward set and reverse reset operations through a unified architecture. The first and second decoder stages, combined with the polarity control mechanism, enable the same circuit to generate both active-high and active-low outputs selectively, eliminating the need for separate decoder circuits for each polarity mode and thereby reducing overall complexity.
Solution Approach 2:
The decoder circuit incorporates dynamic polarity control that allows it to adapt its output mode based on operational requirements. The polarity control signals dynamically switch the inversion state of the second decoder stage, enabling the circuit to transition between different output polarities as needed, which simplifies the design compared to having fixed separate decoders for each mode.
Data Source
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AI summary
A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.