Reversible Polarity Decoder Circuit for 3D Memory Arrays
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Solution Overview
Problem
In semiconductor memory arrays, especially in 3D technology, the high voltages required for programming and erasing passive element memory cells pose a challenge due to the limitations of high-voltage transistors, which do not scale well with decreasing word line and bit line pitches, leading to breakdown issues in decoder circuits.
Innovation Solution
A decoder circuit design that utilizes dual polarity row decoders with specific biasing conditions and coupling circuits to manage voltage across selected and unselected word lines and bit lines, allowing for efficient operation near the breakdown voltage of transistors, thereby preventing breakdown and enabling scalable memory array designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If high voltage transistors are used to achieve the required voltage swing for programming and erasing memory cells, then the voltage requirement is met, but the transistor size and area increase significantly
Solution Approach 1:
The decoder output driver circuit is segmented into multiple coupling circuits (first coupling circuit, second coupling circuit, third coupling circuit) that operate in series. Each coupling circuit handles a portion of the total voltage swing, allowing standard low-voltage transistors to achieve the required high voltage output by dividing the voltage stress across multiple components.
Solution Approach 2:
The circuit transitions from a single-transistor high-voltage approach to a multi-circuit series configuration, effectively adding dimensional complexity to the voltage delivery path. This allows the system to achieve high voltage swing through structural arrangement rather than relying on individual high-voltage transistor characteristics.
2Strength
If high voltage transistors are used to provide sufficient voltage across selected memory cells, then programming and erasing operations are enabled, but the transistors do not scale well with decreasing word line and bit line pitches
Solution Approach 1:
The voltage delivery function is segmented across multiple coupling circuits rather than relying on a single high-voltage transistor. This segmentation allows each circuit element to use standard-voltage transistors that scale properly with technology, while the series combination achieves the required high voltage output.
Solution Approach 2:
The solution moves from a vertical scaling approach (using higher voltage transistors) to a horizontal expansion approach (using multiple standard transistors in series). This dimensional shift enables the circuit to maintain scalability with decreasing pitch while achieving the necessary voltage output through structural configuration.
3Loss of energy
If the decoder operates at breakdown voltage to maximize voltage swing, then power efficiency is improved, but transistor breakdown occurs without proper protection
Solution Approach 1:
The circuit incorporates protection mechanisms that prevent voltage across any single coupling circuit from exceeding transistor breakdown voltages. By distributing and limiting the voltage stress beforehand through the series configuration and control logic, the system can operate efficiently near breakdown voltages without causing actual breakdown events.
Solution Approach 2:
The coupling circuits act as intermediary elements between the decoder logic and the memory array. These intermediaries control and distribute the voltage swing, ensuring that no single transistor experiences excessive voltage stress while still enabling the overall system to achieve the required high voltage output for efficient operation.
4Adaptability or versatility
If dual polarity decoder outputs are implemented to support both active low and active high modes, then memory array functionality is improved, but voltage breakdown problems occur in transmission gate circuits
Solution Approach 1:
The dual polarity decoder output is segmented into multiple coupling circuits that can be independently controlled for each polarity mode. This segmentation allows the circuit to switch between active low and active high modes while distributing the voltage stress appropriately in each mode, preventing breakdown in transmission gate circuits.
Solution Approach 2:
The circuit dynamically adapts its configuration based on the required polarity mode. The coupling circuits can be selectively activated or deactivated depending on whether active low or active high output is needed, allowing the system to maintain reliability across both operational modes while preserving full functionality.
Data Source
AI summary
A reversible polarity decoder circuit is disclosed which is particularly suitable for implementing a multi-headed decoder structure, such as might be used for decoding word lines, and particularly in a 3D memory array. The decoder circuit provides an overdrive voltage bias to the gates of half-selected word line driver circuits to solidly maintain the half-selected word lines at an inactive level. If the memory array is biased at or near the breakdown voltage, this overdrive voltage may be greater than the breakdown voltage of the decoder transistors. However, in the embodiments described, the decoder circuit accomplishes this without impressing a voltage greater than the breakdown voltage across any of the decoder transistors, for either polarity of operation of the decoder circuit.