Rewind Structural Verification for Retimed Multi-Clock Circuits
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Solution Overview
Problem
Current methods for verifying structural correctness in retimed circuits are inefficient, particularly in handling complex systems with millions of gates and megabits of embedded memory, as they require extensive computational resources and time, and struggle with formal verification of equivalence between original and retimed circuits.
Innovation Solution
A method and apparatus for rewind structural verification, where the retimed circuit is reverse-engineered to determine if it can be retimed back to the original circuit by solving for retiming labels, ensuring structural correctness through constrained random simulation and bounded sequential logic simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If formal verification is used to verify structural correctness of retimed circuits, then verification accuracy is improved, but computational complexity and verification time increase significantly
Solution Approach 1:
The verification process is segmented into multiple passes: a first pass using constrained random simulation to quickly identify obvious structural errors, followed by a second pass using bounded sequential logic simulation only on circuits that pass the first pass. This segmentation allows the system to maintain high verification accuracy while reducing overall computational complexity by avoiding expensive formal verification on all circuits.
Solution Approach 2:
The patent applies partial verification action by using constrained random simulation as a preliminary filter before applying more rigorous bounded sequential logic simulation. This partial action approach verifies only the most critical structural aspects first, then applies deeper verification only where needed, thereby reducing total computational complexity while maintaining sufficient verification accuracy.
2Measurement precision
If formal verification is used to verify structural correctness of retimed circuits, then verification accuracy is improved, but verification time increases significantly
Solution Approach 1:
The verification process is segmented into multiple passes: a first pass using constrained random simulation to quickly identify obvious structural errors, followed by a second pass using bounded sequential logic simulation only on circuits that pass the first pass. This segmentation allows the system to maintain high verification accuracy while reducing overall verification time by avoiding expensive formal verification on all circuits.
Solution Approach 2:
The patent applies partial verification action by using constrained random simulation as a preliminary filter before applying more rigorous bounded sequential logic simulation. This partial action approach verifies only the most critical structural aspects first, then applies deeper verification only where needed, thereby reducing total verification time while maintaining sufficient verification accuracy.
3Reliability
If comprehensive structural verification is performed on large circuits with millions of gates, then verification thoroughness is improved, but computational resources required increase
Solution Approach 1:
The verification process is segmented into multiple passes with increasing thoroughness: a first pass using constrained random simulation that requires minimal computational resources to catch obvious errors, followed by a second pass using bounded sequential logic simulation on a reduced set of circuits. This segmentation enables comprehensive verification of critical paths while managing computational resource requirements.
Solution Approach 2:
The patent applies partial verification action by using constrained random simulation as a preliminary filter before applying more resource-intensive bounded sequential logic simulation. This approach performs thorough verification only where necessary, reducing total computational resources required while maintaining verification reliability for the final retimed circuit.
Data Source
AI summary
A method for designing a system on a target device includes performing register retiming on an original design for the system to generate a retimed design. The retimed design is verified to determine whether it is structurally correct by performing a plurality of iterations of register retiming on the retimed design, wherein each iteration accounts for the register retiming of registers in the system driven by a different clock.