Rewritable Configuration Memory Circuit for FPGA Soft Error Resistance
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Solution Overview
Problem
Reconfigurable semiconductor integrated circuits like FPGAs face soft errors due to high-energy particles or noise in SRAM-based configuration memory, which can lead to malfunctions, and nonvolatile memory solutions like flash memory increase costs and limit reconfigurability during development stages.
Innovation Solution
A configuration memory circuit design using a specific arrangement of transistors and wiring lines that allows for rewritable memory cells, reducing the risk of soft errors and enabling cost-effective production while maintaining reconfigurability, utilizing a memory cell structure with p-channel and n-channel MOS transistors connected in series and parallel configurations to manage bit and word lines effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If SRAM cells are used in configuration memory, then reconfigurability and low cost are maintained, but soft errors occur due to high-energy particles or noise
Solution Approach 1:
The configuration memory is divided into two distinct regions: a first region using SRAM cells for reconfigurable logic elements and a second region using nonvolatile memory cells for configuration data storage. This segmentation allows each region to serve its specific function with appropriate characteristics, resolving the contradiction between reconfigurability and soft error resistance.
Solution Approach 2:
A memory interface circuit acts as an intermediary between the nonvolatile memory cells and the logic elements. This interface circuit retrieves configuration data from the nonvolatile memory and supplies it to the logic elements, enabling the system to benefit from both the nonvolatile memory's soft error resistance and the logic elements' reconfigurability.
2Reliability
If flash memory cells are used in configuration memory, then soft errors are avoided, but manufacturing costs increase due to mixed CMOS and flash memory processes
Solution Approach 1:
The configuration memory is divided into two distinct regions: a first region using SRAM cells for reconfigurable logic elements and a second region using nonvolatile memory cells for configuration data storage. This segmentation allows each region to serve its specific function with appropriate characteristics, resolving the contradiction between reconfigurability and soft error resistance.
Solution Approach 2:
Different memory cell types are used in different regions of the configuration memory based on local requirements. The second region uses nonvolatile memory cells specifically where soft error resistance is critical for configuration data, while the first region uses SRAM cells where reconfigurability is needed. This local differentiation optimizes both reliability and cost.
3Ease of manufacture
If anti-fuse elements are used in configuration memory, then manufacturing cost is reduced and soft errors are avoided, but reconfigurability is lost due to inability to rewrite
Solution Approach 1:
The configuration memory is divided into two distinct regions: a first region using SRAM cells for reconfigurable logic elements and a second region using nonvolatile memory cells for configuration data storage. This segmentation allows each region to serve its specific function with appropriate characteristics, resolving the contradiction between reconfigurability and soft error resistance.
Solution Approach 2:
The system provides dynamic reconfigurability through the first region using SRAM cells and nonvolatile memory cells, allowing the logic elements to be reconfigured during development and testing. The nonvolatile nature of the second region ensures that once configured, the settings are retained without power, combining both rewritability and cost-effectiveness.
Data Source
AI summary
A configuration memory circuit according to an embodiment includes: a first and second wirings; and a first to eighth transistors, the first and fourth transistors having a first-conductive-type, the second, third, fifth, and sixth transistors having a second-conductive-type, the first to third transistors being connected in series, the fourth to sixth transistors being connected in series, gates of the first and third transistors being connected to the first wiring, one of a source and a drain of the seventh transistor, and the first wiring, a gate of the second transistor being connected to a third wiring, gates of the fourth and sixth transistors being connected to the second wiring, one of a source and a drain of the eighth transistor, and the second wiring, a gate of the fifth transistor being connected to the third wiring, gates of the seventh and eighth transistors being connected to a fifth wiring.