REX2 EVEX2 Prefixes Enhance 64-bit Code Density
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Solution Overview
Problem
Existing processor architectures lack efficient mechanisms to enhance code density and support advanced performance extensions (APX) in 64-bit execution mode, particularly in handling new data destinations and flag suppression, which limits instruction set architecture (ISA) flexibility and performance.
Innovation Solution
The introduction of new prefixes, such as REX2 and EVEX2, which provide enhanced encoding capabilities for opcode maps, support 32 general-purpose registers, and enable flag suppression, allowing for improved code density and APX features by modifying instruction formats and adding new functionalities like new data destinations and per-logical-processor speculation controls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional prefixes are used to modify instructions, then instruction format compatibility is maintained, but code density and ISA flexibility are limited
Solution Approach 1:
The prefix structure is segmented into multiple bytes (e.g., REX2 prefix with multiple fields, EVEX2 prefix with four bytes containing opcode map, data destination, and flag suppression fields). This segmentation allows independent control of different instruction aspects, enabling enhanced adaptability without overwhelming complexity.
Solution Approach 2:
The patent extends the traditional single-byte prefix into multi-byte prefix structures (REX2, EVEX2) that add dimensional depth to instruction encoding. This allows encoding of additional functionalities like 32 general-purpose registers, new data destinations, and flag suppression in new dimensions of the instruction format.
2Productivity
If more instructions and memory operations are used, then functionality is achieved, but processor performance decreases due to allocation stalls
Solution Approach 1:
The prefix structures (REX2, EVEX2) encode speculation control information in advance, allowing the processor to pre-determine execution paths and allocate resources beforehand. This preliminary encoding of control information eliminates runtime allocation stalls by preparing execution parameters ahead of time.
Solution Approach 2:
The instruction prefixes contain self-contained control information for speculation management and resource allocation. The processor can autonomously interpret these prefix fields to manage its own execution flow without external intervention, reducing allocation overhead and improving productivity.
Data Source
AI summary
Techniques for push or pop operations using a single instruction are described. An example instruction at least include a prefix, one or more fields to identify a first source operand location, one or more fields to identify a second source operand location, and an opcode to indicate execution circuitry is to do push data from the identified first source operand and the identified second source operand onto a stack, wherein a payload of the prefix to provide most significant bits to identify at least one of the first and second source operand locations.