Hybrid Class-AB RF ADC Amplifier for Bandwidth and Linearity

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Solution Overview

Problem

High-performance RF ADCs require high bandwidth, high linearity, and low noise input amplifiers, but existing Class-A and Class-AB unity gain buffers face challenges in power consumption, linearity, and bandwidth limitations, especially at high frequencies, which affect the overall signal chain performance.

Innovation Solution

A hybrid Class-AB amplifier architecture combining common-gate and common-source transistor devices in parallel current paths, with complementary operation and current reuse, to enhance bandwidth, linearity, and reduce power consumption, while providing adjustable gain and improved isolation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If Class-A unity gain buffer is used, then linearity is improved, but power consumption increases and bandwidth is limited

Engineering Contradiction:

ImprovelinearityVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The amplifier is divided into two parallel paths: a Class-AB path for high-linearity signal processing and a Class-C path for bandwidth extension and power efficiency. This segmentation allows each path to be optimized for its specific function while working together to achieve overall system goals.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The system dynamically switches between Class-AB and Class-C operation modes based on signal conditions. The Class-C amplifier is activated to extend bandwidth when needed, while the Class-AB path maintains linearity for high-quality signal processing, creating a dynamic hybrid operation mode.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If Class-AB unity gain buffer is used, then power consumption is reduced, but bandwidth is limited at high frequencies

Engineering Contradiction:

Improvepower consumptionVSAvoidbandwidth

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent merges Class-AB and Class-C amplifier architectures into a hybrid configuration where both paths process signals in parallel. The Class-AB path provides power-efficient operation while the Class-C path extends bandwidth, and their outputs are combined to achieve both low power consumption and high bandwidth simultaneously.

Inventive Principle:

Principle #5Merging (Combining)

3Measurement precision

If more complex circuit design is implemented, then linearity is improved, but device complexity increases

Engineering Contradiction:

ImprovelinearityVSAvoidcircuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The system employs periodic switching between Class-AB and Class-C operation modes to maintain high linearity performance. By alternating between the two modes based on signal characteristics, the system achieves improved linearity without requiring a permanently complex circuit design, as the complexity is activated only when needed.

Inventive Principle:

Principle #19Periodic action

Data Source

PatentUS11437963B2Amplifiers for RF ADCS

Publication Date: 2022.09.06 ANALOG DEVICES INT UNLTD CO

AI summary

High-performance radio frequency analog-to-digital converters (RF ADCs) demand high bandwidth, high linearity, and low noise input amplifiers. A Class-AB amplifier, including common-gate transistor devices and common-source transistor devices operating in parallel, offers high bandwidth and high linearity, while offering lower power operation when compared to Class-A amplifiers. The Class-AB amplifier can be followed by a Class-AB unity gain buffer comprising common-source transistor devices to provide additional isolation for the RF ADC from the circuitry preceding the Class-AB amplifier.