RF Power Amplifier Harmonic Suppression Using Back-Hole Resonance
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Solution Overview
Problem
Traditional radio frequency power amplifiers have limited capability to suppress high-order harmonics, despite improvements in low-order harmonic suppression, which leads to interference in other channels.
Innovation Solution
A circuit structure is introduced that includes a resonant network with a capacitor and a back hole to suppress high-order harmonics, and a low-order harmonic suppression unit with multiple inductors and capacitors to effectively suppress second, third, and fourth harmonics, all integrated on a chip Die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a low-pass three-section LC matching structure is used for output matching, then the basic matching function is achieved, but the capability to suppress high-order harmonics remains limited
Solution Approach 1:
The patent divides the harmonic suppression function into two segments: a low-order harmonic suppression network (for 2nd, 3rd, 4th harmonics) and a high-order harmonic suppression network (for 5th and higher harmonics). Each segment uses different circuit topologies optimized for its specific frequency range, allowing both low-order and high-order harmonics to be suppressed effectively without requiring a single complex structure to handle all frequencies.
Solution Approach 2:
The patent implements nesting by integrating the high-order harmonic suppression network within the existing low-pass LC matching structure. The high-order suppression network is embedded in the output matching circuit, while the low-order suppression network is added in parallel. This nested arrangement allows the new harmonic suppression functions to be incorporated without completely redesigning the original matching network, thus controlling device complexity.
2Object-generated harmful factors
If a harmonic suppression network is added into the chip Die, then low-order harmonic suppression capability is improved, but the capability to suppress high-order harmonics remains limited and chip area increases
Solution Approach 1:
The patent applies local quality by using different circuit configurations for different harmonic ranges. The low-order suppression network uses LC parallel resonant circuits tuned to specific low-order harmonic frequencies (2nd, 3rd, 4th), while the high-order suppression network uses a capacitive divider configuration with a back-hole capacitor. Each local circuit is optimized for its specific frequency range, achieving effective suppression without requiring uniform complex circuitry across the entire chip.
Solution Approach 2:
The patent utilizes the vertical dimension by implementing the high-order harmonic suppression network through a back-hole capacitor structure that extends through the substrate. This three-dimensional approach allows the high-order suppression function to be achieved without occupying additional planar chip area, as the suppression mechanism utilizes the vertical space through the substrate rather than requiring more surface area.
3Object-generated harmful factors
If traditional LC matching network is used, then the circuit structure is simple, but the harmonic suppression effect is insufficient
Solution Approach 1:
The patent merges multiple functions into a unified output matching circuit. The original low-pass LC matching network is combined with the low-order harmonic suppression network (using parallel resonant circuits) and the high-order harmonic suppression network (using capacitive divider with back-hole capacitor). This merged structure achieves both impedance matching and comprehensive harmonic suppression (both low-order and high-order) simultaneously, rather than requiring separate independent circuits for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the harmonic suppression capability of radio frequency power amplifiers, particularly for high-order harmonics, while maintaining a compact chip Die area and simplicity in implementation.
Implementation Method 1
high-order harmonics are suppressed by means of the resonant effect of a capacitor and a back hole
Implementation Method 2
a low-order harmonic suppression unit is electrically connected to the output stage unit to suppress second, third and fourth harmonics
Data Source
AI summary
A circuit structure for improving the harmonic suppression capability of a radio frequency power amplifier includes an output stage unit, a high-order harmonic suppression unit, and a low-order harmonic suppression unit. The output stage unit outputs a signal to be subjected to harmonic suppression; the high-order harmonic suppression unit comprises a first filter capacitor and a back hole, and is used for suppressing fifth or higher harmonics; the output stage unit and the first filter capacitor are connected to the ground in series by means of the back hole; the low-order harmonic suppression unit is connected to the output stage unit to suppress second, third and fourth harmonics. According to the design, the high-harmonic suppression capability of the radio frequency power amplifier is improved.