RF Amplifier Bias Circuit With RF-Sensing Linearization Transistors
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Solution Overview
Problem
Conventional adaptive and linearization biasing techniques for RF amplifiers are sensitive to process, voltage, and temperature variations, have limited envelope bandwidth, and are not optimal for power amplifiers using stacked transistors, particularly in modern communication systems like 5G.
Innovation Solution
The proposed bias arrangement includes separate bias and linearization circuits coupled by a coupling circuit, with linearization transistors configured to sense RF signals and provide modified bias signals at different terminals, reducing sensitivity to PVT variations and improving envelope bandwidth, and is suitable for amplifiers with stacked transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional adaptive and linearization biasing techniques are used, then bias control is achieved, but sensitivity to process, voltage, and temperature variations increases
Solution Approach 1:
The patent divides the conventional single-loop bias arrangement into two separate circuits: a bias circuit and a linearization circuit. This segmentation allows each circuit to be optimized independently, with the bias circuit providing stable bias signals and the linearization circuit compensating for PVT variations, thereby reducing overall sensitivity to process, voltage, and temperature changes.
Solution Approach 2:
The patent introduces a coupling circuit as an intermediary between the bias circuit and the linearization circuit. This coupling circuit mediates the interaction between the two circuits, allowing the linearization circuit to sense RF signals and provide modified bias signals without directly interfering with the bias circuit's stability, thus reducing PVT sensitivity while maintaining bias control.
2Manufacturing precision
If conventional linearization circuits are used, then linearity improvement is achieved, but envelope bandwidth is limited
Solution Approach 1:
By separating the bias circuit from the linearization circuit, the patent allows the linearization circuit to be optimized specifically for bandwidth performance while the bias circuit maintains linearity. The linearization circuit can use wider bandwidth components and topologies without compromising bias stability, thereby increasing envelope bandwidth while preserving linearity improvements.
Solution Approach 2:
The patent makes the linearization circuit dynamic by allowing it to sense RF signals and provide modified bias signals that adapt to changing signal conditions. This dynamic operation enables the linearization circuit to maintain linearity across a wider envelope bandwidth, as it can respond to fast signal variations without being constrained by the slower bias circuit.
3Power
If stacked transistors are used in power amplifiers, then power handling capability is improved, but biasing performance deteriorates
Solution Approach 1:
The patent separates bias generation from linearization functions, allowing the bias circuit to be specifically optimized for stacked transistor configurations. The bias circuit can provide appropriate bias signals for each transistor in the stack, while the linearization circuit handles the challenging task of compensating for nonlinearities in high-power operation, thereby improving overall biasing performance in power amplifiers using stacked transistors.
Data Source
AI summary
Bias arrangements for amplifiers are disclosed. An example arrangement includes a bias circuit, configured to produce a bias signal for the amplifier, and a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal based on an RF signal indicative of an RF input signal to be amplified by the amplifier. The linearization circuit includes a bias signal input for receiving the bias signal, an RF signal input for receiving the RF signal, and an output for providing a modified bias signal. The linearization circuit further includes at least a first linearization transistor, having a first terminal, a second terminal, and a third terminal, where each of the bias signal input and the RF signal input of the linearization circuit is coupled to the first terminal of the first linearization transistor, and the output of the linearization circuit is coupled to the third terminal of the first linearization transistor.