RF Amplifier Transistor Stack with Coupled Gate Capacitor Topology
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Solution Overview
Problem
Existing amplifier circuits with stacked transistors face challenges in achieving practical realization of large stack heights due to decreasing capacitance values of gate capacitors, which become comparable to parasitic/stray capacitances, making it difficult to maintain a desired voltage distribution across transistors, especially as the number of transistors increases.
Innovation Solution
The proposed solution involves a novel gate capacitor topology where gate capacitors of adjacent or non-adjacent transistors are coupled to increase capacitance values, allowing for a desired distribution of RF voltage across the transistors while maintaining efficient operation, thereby enabling the realization of higher stack heights and larger output power or using smaller transistors with smaller withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of transistors in the stack increases to achieve higher output power, then the output power capability is improved, but the capacitance values of gate capacitors decrease to values comparable to parasitic/stray capacitance, making practical realization difficult
Solution Approach 1:
The patent combines multiple gate capacitors in parallel to achieve the required total capacitance value. Specifically, gate capacitors are connected in parallel between the gate and source of cascode transistors, allowing the cumulative capacitance to meet the minimum threshold that exceeds parasitic/stray capacitance while maintaining the desired number of transistors in the stack for high output power capability.
2Stability of the object's composition
If the capacitance value of gate capacitors is reduced to maintain voltage distribution in larger stacks, then the voltage distribution is maintained, but the capacitance becomes comparable to parasitic/stray capacitance, rendering practical realization challenging
Solution Approach 1:
Multiple gate capacitors are connected in parallel to achieve the required total capacitance value. This merging approach allows the design to maintain adequate capacitance values that exceed parasitic/stray capacitance while preserving the desired voltage distribution across the transistor stack, making the circuit practically realizable.
Solution Approach 2:
The patent introduces an additional degree of freedom in capacitor configuration by allowing gate capacitors to be connected to intermediate nodes rather than strictly to ground or source. This dimensional change in the capacitor topology enables flexible capacitance adjustment to maintain voltage distribution while achieving practical capacitance values.
3Stability of the object's composition
If gate capacitors are used to allow gates to float with RF signal, then the voltage distribution across transistors is maintained, but the capacitance values must be precisely controlled, increasing manufacturing difficulty
Solution Approach 1:
By combining multiple gate capacitors in parallel, the total capacitance value becomes less sensitive to individual capacitor variations. This merging approach provides tolerance compensation, where the aggregate capacitance maintains the required value even with manufacturing variations in individual capacitors, reducing the precision requirements for each component.
Solution Approach 2:
The patent uses multiple identical or similar gate capacitors in parallel, creating replicated capacitor units. This copying approach allows for standardized manufacturing of capacitor units with consistent characteristics, and the parallel combination provides redundancy and tolerance compensation, reducing the impact of manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the practical implementation of larger stack heights in RF amplifiers with improved capacitance values that exceed parasitic/stray capacitances, maintaining efficient voltage distribution and performance without sacrificing output power or efficiency.
Implementation Method 1
N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors... at least one gate capacitor of the N gate capacitors is connected, at a second terminal of the at least one gate capacitor, to a first terminal of a coupling gate capacitor
Data Source
AI summary
Systems, methods and apparatus for practical realization of an integrated circuit comprising a stack of transistors operating as an RF amplifier are described. As stack height is increased, capacitance values of gate capacitors used to provide a desired distribution of an RF voltage at the output of the amplifier across the stack may decrease to values approaching parasitic/stray capacitance values present in the integrated circuit which may render the practical realization of the integrated circuit difficult. Coupling of an RF gate voltage at the gate of one transistor of the stack to a gate of a different transistor of the stack can allow for an increase in the capacitance value of the gate capacitor of the different transistor for obtaining an RF voltage at the gate of the different transistor according to the desired distribution.