RF Amplifier Ground Equalization for Accurate IDD Calibration

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Solution Overview

Problem

During automated test equipment (ATE) testing of RF integrated circuits, the increased resistance of test probes leads to inaccurate IDD calibration, resulting in reduced IC yield due to differences in ground voltages between the bias network and active circuit, causing higher current values when assembled into modules, which fail to meet specifications.

Innovation Solution

Incorporating an on-chip calibration switch or active feedback loop calibration circuit to equalize voltages between the bias network and active circuit during ATE testing, allowing for accurate IDD calibration without affecting noise performance during normal operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If automated test equipment with test probes is used to measure IDD current during calibration, then testing capability is enabled, but the increased resistance of test probes causes inaccurate calibration results

Engineering Contradiction:
Improveautomated testing capabilityVSAvoidIDD calibration accuracy
Core Design Contradiction:
Extent of automationVSMeasurement precision

Solution Approach 1:

A calibration switch is introduced as an intermediary component connected between the bias network ground and the active circuit ground. During calibration, the switch closes to create a common ground reference, eliminating the measurement error caused by probe resistance. This intermediary structure allows accurate calibration despite the presence of high-impedance test probes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The calibration switch is activated before the actual IDD measurement and calibration process. By closing the switch to equalize ground voltages prior to measurement, the system prepares the circuit in a known state that compensates for the inherent probe resistance, ensuring accurate calibration results from the outset.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If test probe resistance is present during calibration, then testing can proceed, but ground voltage differences cause incorrect current calibration

Engineering Contradiction:
Improvetesting throughputVSAvoidcurrent calibration accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The calibration switch creates a feedback path that allows the bias network and active circuit to reference a common ground potential during calibration. This feedback mechanism continuously equalizes ground voltages, ensuring that the IDD calibration reflects the actual operating conditions without the error introduced by probe resistance.

Inventive Principle:
Principle #23Feedback

3Device complexity

If calibration is performed without ground equalization, then testing is simpler, but modules fail to meet specifications after assembly

Engineering Contradiction:
Improvecalibration circuit complexityVSAvoidspecification compliance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The calibration function is segmented from normal operation. The calibration switch is only activated during the calibration phase and remains open during normal circuit operation. This segmentation allows the additional ground equalization circuitry to be included without permanently increasing the complexity of the operational circuit, while ensuring specification compliance through accurate calibration.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20240275336A1Integrated Circuit Yield Improvement
Publication Date: 2024.08.15 PSEMI CORP
  • US20240275336A1 patent drawing
  • US20240275336A1 patent drawing
  • US20240275336A1 patent drawing

AI summary

Circuits and methods for improving IC yield during automated test equipment (ATE) calibration of circuit designs which require IDD calibration and use a closed feedback bias circuit, such as amplifier circuits. The circuit designs include bias branch/active circuit architectures where the active circuit includes one or more active devices. An example first embodiment uses an on-chip calibration switch between the on-chip grounds of a bias network and an active circuit comprising an amplifier. During calibration of the active circuit by the ATE, the calibration switch is closed, and after completion of calibration, the calibration switch is opened. An example second embodiment utilizes an active on-chip feedback loop calibration circuit to equalize voltages between the on-chip grounds of a bias network and an active circuit comprising an amplifier during calibration of the active circuit. Both embodiments mitigate or overcome miscalibration of active circuit current settings resulting from ATE test probe resistance.