RF Amplifier Module With Integrated Impedance Matching Circuit
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Solution Overview
Problem
High power RF semiconductor devices using wirebond arrays face issues with inductive coupling and complex, costly assembly processes, leading to performance and cost challenges due to the inclusion of wirebond arrays in RF amplifiers.
Innovation Solution
The implementation of high-Q impedance matching circuits on semiconductor substrates with patterned back metal, eliminating the need for wirebond arrays by using physically separated input, output, and ground ports, and integrating inductors and capacitors on a single semiconductor die to reduce manufacturing costs and enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wirebond arrays are used to achieve high-Q inductors for impedance matching, then the quality factor is improved, but inductive coupling between device components occurs and assembly complexity increases
Solution Approach 1:
The patent merges the inductor and capacitor functions into a single integrated impedance matching circuit fabricated directly on the semiconductor die using standard CMOS fabrication processes. This eliminates the need for separate wirebond arrays to provide inductance, as the inductors are formed as planar spiral structures integrated with the capacitive elements on the same substrate, thereby reducing assembly complexity while maintaining high-Q performance.
Solution Approach 2:
The patent replaces the mechanical wirebond array system with an integrated circuit implementation where inductors are formed as planar spiral patterns on the semiconductor die. This substitution eliminates the mechanical assembly of wirebonds and their associated inductive coupling problems, while achieving the same electrical function through fabricating inductors using standard semiconductor fabrication techniques.
2Manufacturing precision
If wirebond arrays are used to provide inductance for impedance matching, then the desired inductance values are achieved, but manufacturing costs increase due to complex back-end assembly processes
Solution Approach 1:
The patent combines the impedance matching circuitry with the semiconductor device fabrication process itself, forming inductors and capacitors as integrated structures on the same die using standard CMOS processes. This eliminates the need for separate wirebond array attachment equipment and complex back-end assembly steps, thereby reducing manufacturing costs while maintaining precise control over inductance values through fabrication process parameters.
Solution Approach 2:
The patent replaces the expensive mechanical wirebond array attachment process with an integrated circuit fabrication approach where inductors are formed as planar spiral structures using standard semiconductor manufacturing techniques. This substitution eliminates the need for specialized back-end assembly equipment and reduces manufacturing costs while achieving the required inductance precision through controlled fabrication parameters.
3Loss of energy
If wirebond arrays are used to achieve high-Q factors, then amplifier efficiency is improved, but inductive coupling between components degrades performance
Solution Approach 1:
The patent merges the inductive and capacitive elements into a single integrated impedance matching circuit on the semiconductor die. By forming inductors as planar spiral structures in close integration with capacitors, the design achieves high-Q factors while minimizing inductive coupling between separate components, as all elements are fabricated as part of the same integrated structure with controlled spatial relationships.
Solution Approach 2:
The patent replaces the wirebond array system that causes inductive coupling between components with an integrated circuit implementation where inductors are formed as planar spiral patterns on the die. This substitution eliminates the harmful inductive coupling between separate wirebond arrays while maintaining high-Q performance through the integrated structure's controlled geometry and proximity to capacitive elements.
Data Source
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AI summary
An amplifier module includes a module substrate. Conductive interconnect structures and an amplifier device are coupled to a top surface of the module substrate. The interconnect structures partially cover the module substrate top surface to define conductor-less areas at the top surface. The amplifier device includes a semiconductor substrate, a transistor, a conductive feature coupled to a bottom surface of the semiconductor substrate and to at least one of the interconnect structures, and a filter circuit electrically coupled to the transistor. The conductive feature only partially covers the semiconductor substrate bottom surface to define a conductor-less region that spans a portion of the bottom surface. The conductor-less region is aligned with at least one of the conductor-less areas at the module substrate top surface. The filter circuit includes a passive component formed over a portion of the semiconductor substrate top surface that is directly opposite the conductor-less region.