RF Chip Capacitor Series Structure for Parasitic Reduction
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Solution Overview
Problem
RF circuitry operating at high frequencies and high power faces challenges in achieving improved accuracy, efficiency, and performance due to parasitic effects from small capacitors and their interconnects.
Innovation Solution
A thin-film, metal-insulator-metal (MIM) chip capacitor structure with a series connection of capacitors, symmetrically arranged without vias or contacts, and configured for flip-chip mounting to minimize parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If small capacitors are used in RF circuitry operating at high frequencies and high power, then the circuit can be compact, but parasitic effects increase reducing accuracy and performance
Solution Approach 1:
The patent divides a single capacitor into multiple smaller capacitor units connected in series. This segmentation allows the overall capacitor to achieve the desired capacitance value while each individual unit remains small enough to minimize parasitic effects. The series connection of multiple smaller capacitors reduces the parasitic inductance and resistance compared to a single large capacitor, thereby improving accuracy and performance in RF circuitry.
2Ease of manufacture
If traditional interconnect structures such as vias and contacts are used to connect capacitors, then manufacturing is simplified, but parasitic inductance and resistance increase
Solution Approach 1:
The patent merges the capacitor units and their interconnections into a single integrated structure formed using standard semiconductor fabrication processes. The capacitor units are connected through shared metal layers and insulating materials within the same fabrication sequence, eliminating the need for separate via and contact structures. This integration maintains manufacturing simplicity while significantly reducing parasitic inductance and resistance by removing discrete interconnect elements.
3Ease of manufacture
If bond wires are used for mounting capacitors, then packaging is simplified, but resistive and inductive parasitic effects increase
Solution Approach 1:
The patent extracts and eliminates bond wires from the capacitor structure by implementing flip-chip mounting technology. The capacitor is mounted directly to the substrate or circuit board through solder bumps or other direct attach methods, removing the bond wire interconnects that introduce resistive and inductive parasitics. This extraction of the harmful bond wire element maintains packaging simplicity while dramatically reducing parasitic effects.
4Object-generated harmful factors
If larger capacitors are used to minimize parasitic effects, then parasitic inductance and resistance decrease, but the capacitance value may not meet design requirements
Solution Approach 1:
The patent changes the electrical parameters by connecting multiple smaller capacitor units in series rather than using a single large capacitor. This parameter change allows the overall structure to achieve the desired equivalent capacitance value while each individual unit remains small enough to minimize parasitic effects. The series connection configuration transforms the relationship between capacitor size and capacitance value, enabling simultaneous optimization of both parameters.
Data Source
AI summary
A radio frequency (RF) chip capacitor circuit and structure are provided. The circuit and structure include a plurality of capacitors connected in series. Each capacitor of the plurality includes a first plate formed from a first metal layer and a second plate formed from a second metal layer. A first two adjacent capacitors of the plurality include first plates formed in a first contiguous portion of the first metal layer or second plates formed in a second contiguous portion of the second metal layer. Each capacitor of the plurality may include a dielectric layer disposed between the first plate and the second plate.