RF Chip Clock Synchronization Using PLL Feedback and Dual-Port RAM
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Solution Overview
Problem
In 5G massive MIMO antenna systems, existing technologies face challenges in achieving synchronization among multiple RF chips and channels, leading to delays that exceed the required 20 ns, affecting synchronous data reception and output.
Innovation Solution
A device and method utilizing a synchronization circuit with a phase-locked loop (PLL) circuit, frequency divider, phase difference calculation, and phase synchronization control to adjust the high-frequency signal, ensuring work clock synchronization among RF chips, and dual-port RAM for data synchronization among channels, ensuring consistent data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock distribution methods are used among multiple RF chips, then device complexity is reduced, but clock phase asynchronization occurs leading to delay differences exceeding 20 ns
Solution Approach 1:
The patent implements a feedback mechanism where the delay difference detection unit continuously monitors the phase difference between reference clock signals from different RF chips. When the delay difference exceeds the threshold (20 ns), the phase synchronization control unit adjusts the PLL circuit to correct the phase difference. This closed-loop feedback ensures synchronization accuracy while managing system complexity through intelligent control.
Solution Approach 2:
The patent introduces a synchronization circuit as an intermediary component between multiple RF chips. This circuit includes a reference clock signal source that distributes synchronized clock signals to all RF chips, and a delay difference detection unit that acts as a mediator to monitor and report phase differences. This intermediary structure centralizes synchronization management, improving reliability without proportionally increasing overall system complexity.
2Speed
If frequency multiplication is performed to generate high-frequency signals, then data transmission speed is improved, but clock phase asynchronization and delay differences increase
Solution Approach 1:
The patent applies preliminary action by synchronizing the phase of reference clock signals before they enter the frequency multiplication stage. The phase synchronization control unit adjusts the PLL circuits of different RF chips in advance to ensure their reference clock signals are phase-aligned. This preliminary synchronization prevents phase asynchronization from propagating through the frequency multiplication process, maintaining both high speed and reliability.
Solution Approach 2:
The patent implements feedback control where the delay difference detection unit continuously monitors phase differences after frequency multiplication. When delay differences exceed the 20 ns threshold, the phase synchronization control unit sends correction signals to adjust the PLL circuits. This feedback mechanism ensures that even with high-frequency signal generation, clock phase synchronization is maintained, resolving the contradiction between speed and reliability.
3Adaptability or versatility
If multiple channels operate independently in a single RF chip, then channel versatility is improved, but data asynchronization occurs among channels
Solution Approach 1:
The patent applies universality by designing a synchronization circuit that serves multiple channels simultaneously. The reference clock signal source and phase synchronization control unit are shared resources that distribute synchronized clock signals to all channels within an RF chip. This multi-functional approach allows channels to operate independently (maintaining versatility) while being governed by a common synchronization mechanism (ensuring data synchronization reliability).
Solution Approach 2:
The patent implements feedback control for multi-channel synchronization where the delay difference detection unit monitors phase differences across all channels. When asynchronization is detected in any channel, the phase synchronization control unit adjusts the PLL circuit to restore synchronization. This feedback mechanism ensures that channel independence does not compromise data synchronization, maintaining both versatility and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively synchronizes clock phases and data transmission across multiple RF chips and channels, meeting the requirement for synchronous data input and output, thereby guaranteeing consistent data transmission speed and reducing clock phase asynchronization issues.
Implementation Method 1
a phase-locked loop (PLL) circuit, configured to receive a reference clock signal, and output a high-frequency signal with a frequency n times that of the reference clock signal
Implementation Method 2
a frequency divider circuit, configured to divide the frequency of the high-frequency signal output by the PLL circuit to obtain a work clock signal with a frequency required by a chip
Implementation Method 3
sampling the phase difference between the reference clock signal and the work clock signal by using the high-frequency signal output by the PLL circuit to obtain a minimum difference between a reference clock edge and a work clock edge
Implementation Method 4
writing the data into a dual-port random access memory (RAM), and allowing the plurality of channels to read the data in the RAM synchronously
Data Source
AI summary
Disclosed are a device and method for realizing data synchronization. The device may include a synchronization circuit for a plurality of radio frequency (RF) chips, configured to realize work clock synchronization among the plurality of RF chips; and/or, a synchronization circuit for a plurality of channels in a single chip, configured to realize data synchronization among the plurality of channels in the single chip.