High-Frequency Chip Interconnect Layout for Alignment-Tolerant Wiring
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Solution Overview
Problem
High-frequency device manufacturing methods face challenges in reducing costs due to poor alignment accuracy between chips and transmission lines, leading to increased electrode sizes and costs.
Innovation Solution
A method involving the mounting of chips with pillars on a metal base, forming an insulator layer, exposing pillar surfaces, and creating wirings connected to these pillars for high-frequency signal transmission, which includes using through holes and electrodes to connect chips and the metal base, thereby reducing costs by optimizing chip and electrode sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bonding wire is used to electrically connect semiconductor chip to pattern on insulating frame, then electrical connection is achieved, but alignment accuracy deteriorates and electrode sizes must be increased
Solution Approach 1:
The patent segments the electrical connection function into multiple components: bonding wire for primary connection and via holes with conductive plugs for secondary connection. This segmentation allows the bonding wire to be smaller since it doesn't need to compensate for alignment errors alone, while the via holes provide additional connection points that tolerate position variations.
Solution Approach 2:
The patent introduces via holes filled with conductive material as intermediary connection elements between the bonding wire and the underlying conductive patterns. These via holes act as mediators that tolerate alignment variations, allowing the bonding wire to connect to multiple via holes even when positioning is not perfectly accurate, thereby reducing the required electrode size on the chip.
2Reliability
If electrode sizes are increased to compensate for poor alignment accuracy, then connection reliability improves, but manufacturing cost increases
Solution Approach 1:
The connection path is segmented into multiple shorter segments (bonding wire to via hole, via hole to conductive pattern) rather than requiring a single large electrode to span the entire connection distance. This segmentation allows each component to be smaller while maintaining overall connection reliability through the distributed connection points.
Solution Approach 2:
The patent adds a vertical dimension to the connection structure by forming via holes that extend through the insulating frame. This third dimension provides additional connection pathways without increasing the horizontal electrode size on the chip surface, thereby maintaining reliability while reducing manufacturing cost.
3Manufacturing precision
If chip mounting position deviates from target position, then alignment accuracy deteriorates, but high-frequency characteristics can be maintained through alternative connection structure
Solution Approach 1:
The patent creates a dynamic connection system where the bonding wire can flexibly connect to multiple via holes at different positions. This dynamic connectivity allows the system to adapt to position deviations, maintaining high-frequency characteristics even when the chip mounting position varies from the target position, as the wire can naturally route to the nearest via holes.
Data Source
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AI summary
A method of manufacturing a high-frequency device includes mounting a first chip having a first pillar on an upper surface thereof on a metal base, forming an insulator layer covering the first chip on the metal base, exposing an upper surface of the first pillar from the insulator layer, and forming a first wiring connected to the first pillar on the insulator layer and transmitting a high-frequency signal.