RF Chip Isolator Design to Reduce Parasitic Capacitance
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Solution Overview
Problem
Radio frequency chips in communication devices face performance issues due to parasitic capacitance between on-chip inductors and substrates, which couples noise and affects inductor performance.
Innovation Solution
Incorporating an isolator between the substrate and on-chip inductor that prevents parasitic capacitance by not generating loop-induced currents in the magnetic field, using structures like notched planar or fishbone designs to isolate effectively and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an isolator is added between the substrate and on-chip inductor to reduce parasitic capacitance, then the parasitic capacitance is reduced, but the device complexity increases
Solution Approach 1:
An isolator is introduced as an intermediary component between the substrate and the on-chip inductor. This isolator specifically targets and eliminates parasitic capacitance pathways while maintaining magnetic field isolation. The isolator acts as a mediator that prevents harmful electrical coupling without interfering with the desired magnetic coupling between the inductor and substrate, thus resolving the contradiction between reducing parasitic effects and maintaining device simplicity.
Solution Approach 2:
The isolator is designed with a segmented structure featuring notches that divide the continuous conductive path into separate segments. This segmentation prevents the formation of loop-induced currents by breaking the current path, while still maintaining the isolator's primary function of reducing parasitic capacitance. The notched structure achieves complex electromagnetic isolation functions through geometric segmentation rather than adding multiple separate components.
2Ease of manufacture
If the isolator uses a planar structure to prevent parasitic capacitance, then the manufacturing is simplified, but loop induced current may be generated in the magnetic field
Solution Approach 1:
The planar isolator structure is modified by introducing notches that segment the continuous conductive path. This segmentation maintains the ease of manufacturing planar structures while simultaneously preventing loop-induced currents by breaking the closed current loops that would form in the magnetic field. The notched design achieves both manufacturing simplicity and electromagnetic compatibility.
Solution Approach 2:
The isolator employs an asymmetric notched pattern rather than a symmetric continuous structure. This asymmetric design with strategically placed notches disrupts the symmetry required for loop-induced current formation while maintaining effective parasitic capacitance reduction. The asymmetric geometry prevents uniform current circulation paths that would generate harmful loop currents in the magnetic field.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The isolator effectively reduces parasitic capacitance, maintaining on-chip inductor performance and simplifying the design process by eliminating noise coupling and capacitance-related complications.
Implementation Method 1
a parasitic capacitance between an on-chip inductor and a substrate in a radio frequency chip is easily generated
Implementation Method 2
the existence of the parasitic capacitance makes it possible for the noise of other circuits in the radio frequency chip to be coupled to the on-chip inductor through the substrate
Implementation Method 3
the isolator is structured not to generate a loop induced current in the magnetic field of the on-chip inductor
Data Source
AI summary
A radio frequency chip, and a method and apparatus for designing a radio frequency chip, which relates to the technical field of integrated circuits, with a major object to reduce the possibility of generating a parasitic capacitance between an on-chip inductor and a substrate. Herein, the radio frequency chip includes a substrate, an on-chip inductor, and an isolator between the substrate and the on-chip inductor, wherein the isolator is structured not to generate a loop induced current in a magnetic field of the on-chip inductor, and the isolator is configured to prevent a parasitic capacitance from being generated between the substrate and the on-chip inductor.