RF Chip Module Co-Optimization for Wideband Power Matching
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Solution Overview
Problem
Chip performance degrades due to parasitics when RF IC chips are incorporated into packages, especially in high-frequency applications like millimeter wave and terahertz, leading to frequency degradation.
Innovation Solution
A chip-package co-optimization method is employed, where the radio frequency front end is split between the chip and package, using complex power matching to power match differential ports at multiple frequencies within a given bandwidth, reducing chip power requirements and allowing for iterative redesign to scale down on-chip devices and overall chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If RF IC chips are incorporated into a package, then the chip module functionality is achieved, but chip performance degrades due to parasitics
Solution Approach 1:
The radio frequency front end is divided into on-chip and off-chip sections. The on-chip section includes the amplifier with first differential port, while the off-chip section includes the passive device and matching network with second differential port. This segmentation allows the chip to be optimized for active functions while the package handles passive functions, reducing parasitic effects on chip performance.
Solution Approach 2:
A matching network is introduced as an intermediary between the on-chip amplifier and off-chip passive device. This matching network, designed through complex power matching process using port voltage reflection coefficients, serves as a mediator to compensate for parasitic effects and achieve power matching across multiple frequencies within a given bandwidth.
2Productivity
If standard impedance matching is used, then design simplicity is maintained, but power transfer is not optimized across wide bandwidth
Solution Approach 1:
The design transitions from standard fixed impedance matching to dynamic parameter optimization. The matching network is designed to achieve power matching at multiple different frequencies within a given bandwidth by utilizing port voltage reflection coefficients. This parameter change approach optimizes power transfer efficiency across the entire operating bandwidth rather than at a single frequency point.
3Reliability
If complex power matching process is applied, then power transfer is optimized at multiple frequencies, but chip power requirement increases
Solution Approach 1:
The chip-package co-optimization process employs iterative redesign where the chip and package designs are repeatedly optimized together. Given the reduction in chip power requirement achieved through complex power matching, the chip is redesigned to reduce the sizes of on-chip devices (e.g., to reduce transistor size) and thereby reduce overall chip size. This dynamic optimization balances power transfer stability with power consumption.
4Area of stationary object
If on-chip devices are scaled down to reduce chip size, then manufacturing cost decreases, but performance may be compromised
Solution Approach 1:
Passive devices and matching networks are extracted from the chip and placed in the package. This extraction allows the chip to be scaled down by removing non-essential passive components, reducing chip area and manufacturing cost while maintaining performance through the off-chip matching network that compensates for the reduced on-chip device sizes.
Data Source
AI summary
A chip module, including a radio frequency integrated circuit (RFIC) chip and a package, and a method and system for designing the module. Chip and package design are performed so the RF front end (FE) is split between chip and package. The chip includes an amplifier with a first differential port and the package includes a passive device and matching network with a second differential port connected to the first differential port. The second differential port is power matched to the first differential port using complex power matching based on port voltage reflection coefficients in order to achieve improved performance (i.e., a peak power transfer across a bandwidth as opposed to at only one frequency). The power matching process can result in a chip power requirement reduction that allows for device size scaling. Thus, designing the chip and designing the package is iteratively repeated in a chip-package co-optimization process.