RF Chiplet BIST Ring Oscillators for Post-Assembly Test
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Solution Overview
Problem
The assembly of heterogeneous microelectronic circuits, which integrate different materials and manufacturing processes, results in increased costs and reduced yield due to the need for pre-assembly testing, particularly when some circuits have poor yield or are expensive to manufacture.
Innovation Solution
Incorporating built-in self-test (BIST) circuitry, such as ring oscillators, into a host wafer with integrated circuitry to test RF transistor chiplets after assembly, allowing for on-chip testing of DC characteristics, gain, linearity, power handling, and speed, thereby improving yield and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If pre-assembly testing is performed on heterogeneous microelectronic circuits, then manufacturing precision and reliability are improved, but manufacturing cost increases and productivity decreases
Solution Approach 1:
The patent incorporates test circuits and test structures during the fabrication process itself, allowing testing to be performed as part of the manufacturing flow rather than as a separate post-assembly step. This preliminary integration of testing capabilities enables quality verification without requiring additional time or resources after assembly, thereby maintaining high manufacturing precision while avoiding the productivity penalty associated with separate pre-assembly testing
Solution Approach 2:
The patent implements built-in self-test (BIST) circuitry that enables the device to test itself without requiring external test equipment or separate testing facilities. The test circuits are integrated within the chip itself, allowing the device to verify its own functionality during or after fabrication, which eliminates the need for expensive and time-consuming external pre-assembly testing while ensuring manufacturing precision
2Adaptability or versatility
If heterogeneous integration of different materials and manufacturing processes is used, then circuit performance and adaptability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the heterogeneous integration into separate functional modules or circuit blocks, each optimized for specific purposes. By segmenting the complex heterogeneous system into manageable units with standardized interfaces, the patent reduces the overall integration complexity while preserving the performance benefits of using different materials and manufacturing processes for different functions
Solution Approach 2:
The patent introduces intermediary layers or interface structures that facilitate the integration of different heterogeneous components. These intermediaries act as translators or adapters between different material systems and manufacturing processes, reducing the direct complexity of integrating disparate technologies while enabling the desired circuit performance
3Adaptability or versatility
If separate fabrication of active and passive circuits is performed, then manufacturing flexibility and adaptability are improved, but assembly complexity and time consumption increase
Solution Approach 1:
The patent combines the fabrication processes for active and passive circuits into a single integrated manufacturing flow, eliminating the need for separate fabrication steps and subsequent assembly operations. This merging of processes maintains the manufacturing flexibility of using different materials and techniques while dramatically reducing assembly cycle time by performing all fabrication in parallel during a single manufacturing sequence
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The BIST circuitry enables efficient, low-cost testing of RF transistor chiplets, enhancing manufacturing yield and reducing overall assembly costs by identifying and correcting interconnect failures and mismatches, thus ensuring proper electrical connections and performance.
Implementation Method 1
The BIST circuitry may include ring oscillators for testing chiplet transistors
Data Source
AI summary
An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.