RF Transistor Chiplet Integration With Host-Wafer Tuning Circuits
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Solution Overview
Problem
There is a need for an electronic assembly using a host wafer with pre-fabricated integrated circuitry that connects to a microelectronics active chiplet integrated in a through-wafer cavity, to facilitate faster and cost-effective manufacturing of microwave or radio frequency (RF) integrated circuits.
Innovation Solution
The solution involves a host wafer with pre-fabricated interconnects and integrated circuitry, such as passive components, that connect to RF transistor chiplets with interconnection tuning circuits. These chiplets are integrated into cavities of the host wafer, allowing for heterogeneous integration of active and passive semiconductor technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If microelectronic circuits are fabricated separately and assembled together, then testing of all microelectronic circuits can be performed separately and fabrication yields can be improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent divides the complete RF circuit into separate active chiplet (containing transistor) and passive circuit components. These segments are fabricated independently on different substrates using optimized processes for each type, then assembled together. This segmentation enables separate testing and quality control of each component, improving overall fabrication yield while maintaining manageable complexity through standardized interconnection interfaces.
2Reliability
If microelectronic circuits employing different materials and manufacturing processes are combined, then circuit performance can be improved, but manufacturing complexity and integration difficulty increase
Solution Approach 1:
The patent applies local quality by allowing different materials and manufacturing processes to be used in specific local regions - the active chiplet uses materials and processes optimized for transistor fabrication, while the passive circuit uses materials and processes optimized for passive component fabrication. The through-substrate interconnections are designed with specific geometric configurations (conductive vias, trace patterns) that are optimized for their local function of electrical coupling, thus achieving high circuit performance while managing integration through localized optimization rather than uniform approach.
3Productivity
If active device technologies are scaled up, then manufacturing speed can be increased, but cost and cycle time burdens increase
Solution Approach 1:
The patent segments the active device fabrication from the passive circuit fabrication, allowing active devices to be manufactured using high-speed, cost-effective processes on large substrates, then assembled with pre-fabricated passive circuits. This segmentation enables the active device portion to benefit from economies of scale and rapid manufacturing techniques without incurring the same cost and cycle time burdens across the entire circuit, thus improving productivity while controlling costs.
Data Source
AI summary
An electronic assembly has a host wafer having a first circuit including passive devices for the purpose of one of tuning or matching networks. Chiplets are placed in the cavities. At least one chiplet has a second circuit including at least one transistor or switch device and passive tuning circuits including at least one of a stabilization network, a gain boosting network, a power delivery network, or a low-noise network. Electrical interconnects between the chiplets and wafer electrically connect the first circuitry to the second circuitry.