RF Path Clock Delay Control for Harmonic Interference Smearing
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Solution Overview
Problem
In communication systems, the operation of digital blocks based on a clock signal acts as an interference aggressor in the radio frequency spectrum, with harmonics of the clock signal often falling within the bandwidth used for radio frequency communication, thereby reducing the quality of the radio frequency signal.
Innovation Solution
A device and method that introduce variable delays to the clock signal, using a delay circuit controlled by a controller clocked by the modified clock signal, to generate a second clock signal with variable delays, which is then used to control the radio frequency path, thereby reducing the impact of interference from the digital block on the radio frequency spectrum.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a digital block is used to control the radio frequency path based on a clock signal, then the radio frequency path can be controlled, but harmonics of the clock signal interfere with the radio frequency spectrum and reduce signal quality
Solution Approach 1:
The patent applies the Dynamics principle by making the clock signal dynamic through variable delays. The delay circuit introduces time-varying delays to the clock signal, causing the harmonics to move and smear across the frequency spectrum over time rather than remaining stationary at fixed harmonic frequencies. This dynamic approach reduces the amplitude of individual harmonic components in the radio frequency band while maintaining the control functionality.
Solution Approach 2:
The patent applies the Parameter changes principle by modifying the time domain parameters of the clock signal. By changing the delay parameter dynamically through the delay circuit, the frequency domain characteristics of the clock signal harmonics are altered. This parameter modification causes the harmonics to spread in frequency, reducing their harmful impact on the radio frequency spectrum while preserving the control capability.
2Object-affected harmful factors
If variable delays are introduced to the clock signal to reduce harmonic interference, then the quality of the radio frequency signal is improved, but the complexity of the device increases due to the delay circuit
Solution Approach 1:
The patent applies the Intermediary principle by introducing a delay circuit as an intermediary component between the clock signal source and the radio frequency path control. This intermediary element modifies the clock signal characteristics to reduce harmonic interference without directly affecting the radio frequency path itself. The delay circuit acts as a mediator that transforms the problematic clock signal into a more suitable form for RF control.
Solution Approach 2:
The patent applies the Dynamics principle by implementing a controllable delay circuit that can dynamically adjust delay values. This dynamic capability allows the system to optimize the trade-off between signal quality and device complexity by adjusting delay parameters as needed, rather than requiring a permanently complex configuration.
Data Source
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Figure 5C~6
AI summary
According to an embodiment, a device (10) is provided which comprises an interface (11) that receives a first clock signal (ck1). A delay circuit (15) adds variable delays to the first clock signal (ck1) based on a delay control signal (13) to generate a second clock signal (ck2) with variable delays. The delay control (13) signal is generated by a controller (12) clocked by the second clock signal (ck2). The device further comprises a radio frequency path (14). The device (10) controls the radio frequency path (14) based on the second clock signal (ck2).