Digital Clock Generation for RF Interference Mitigation

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Solution Overview

Problem

Modern radio transceivers face significant interference from clock harmonic interference, which affects their ability to receive low power RF signals and requires techniques to minimize this interference while maintaining performance across various frequency bands.

Innovation Solution

The implementation of circuitry that generates a digital clock frequency based on a divided-down carrier signal frequency, allowing interference to occur at harmonics of the carrier signal, which can be easily filtered out, and includes programmable frequency dividers, oscillators, and a fallback oscillator for improved reliability and flexibility.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If digital circuit elements are integrated closely with RF circuit components to achieve high functional integration, then device complexity is reduced and manufacturing cost decreases, but clock harmonic interference increases and RF signal reception performance deteriorates

Engineering Contradiction:
Improvefunctional integrationVSAvoidclock harmonic interference
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the harmful clock harmonic frequencies from the RF signal path by identifying and removing specific frequency components that cause interference. This is achieved through filtering techniques that separate the harmful harmonic frequencies from the desired RF signals, allowing the integrated circuit to maintain both high functional integration and low interference levels

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the frequency parameters of the digital clock to avoid generating harmonics that fall within the RF reception bands. By adjusting the clock frequency and its harmonics to frequencies that do not overlap with operational RF bands, the system maintains high functional integration while minimizing harmful interference through parameter optimization

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the transceiver operates in multiple frequency bands to achieve versatility, then adaptability improves, but the risk of clock harmonic interference increases

Engineering Contradiction:
Improvefrequency band operationVSAvoidharmonic interference
Core Design Contradiction:
Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements dynamic frequency selection where the digital clock frequency is adjusted based on the currently active RF frequency band. This dynamic adaptation allows the system to maintain versatility across multiple frequency bands while continuously optimizing the clock frequency to avoid generating harmful harmonics in any given band, thereby preventing interference through real-time parameter adjustment

Inventive Principle:
Principle #15Dynamics

3Productivity

If digital signal processing capability is increased to achieve high performance, then communication performance improves, but clock harmonic interference increases

Engineering Contradiction:
Improvesignal processing capabilityVSAvoidclock harmonic interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent optimizes the digital clock frequency parameter to achieve a balance between signal processing performance and interference generation. By selecting clock frequencies that provide sufficient processing capability while avoiding frequencies that generate harmful harmonics in operational bands, the system maintains high productivity without excessive interference

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent extracts and removes the harmful harmonic components generated by high-speed digital signal processing from the RF signal path. Through selective filtering and frequency management, the system eliminates the harmful interference while preserving the beneficial high-performance digital signal processing capabilities

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUSRE49526E1Generation of digital clock for system having RF circuitry
Publication Date: 2023.05.09 HUAWEI TECH CO LTD
  • USRE49526E1 patent drawing
  • USRE49526E1 patent drawing
  • USRE49526E1 patent drawing

AI summary

Circuitry for any of a transceiver, a transmitter, and a receiver, has radio frequency (RF) circuitry, digital circuitry, a carrier signal generator to provide a carrier signal to the RF circuitry and a clock generator for generating a digital clock for clocking at least some of the digital circuitry. The RF circuitry is susceptible to interference from harmonics of the clocking, and the clock generator derives a frequency of the digital clock based on a frequency divided down from a frequency of the carrier signal so that the interference to the RF circuitry occurs at frequencies which are harmonics of the carrier signal.