RF Clock Synthesizer Phase Alignment Across Multiple PLLs
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Solution Overview
Problem
Massive MIMO and beamforming wireless transceivers face challenges in maintaining phase coherence across multiple antennas and transceiver units due to temperature variations and power cycles, requiring precise phase control of RF signals, which is complex and costly, and necessitates frequent recalibration.
Innovation Solution
A system and method for phase aligning RF clock signals across multiple PLLs using a dedicated system-wide reference signal, reducing the need for complex clock distribution buffers and improving phase stability over temperature gradients, allowing for less frequent recalibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex clock distribution buffers and precise phase control mechanisms are used to maintain phase coherence across multiple antennas, then phase alignment accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the phase alignment function from complex clock distribution buffers and dedicated phase control circuits. Instead of using separate phase control mechanisms for each antenna, the system uses a single system-wide reference signal that all PLLs lock to, eliminating the need for complex per-antenna phase control hardware while maintaining phase coherence across the antenna array
Solution Approach 2:
The patent merges multiple independent phase control functions into a single unified reference signal distribution system. By having all PLLs synchronize to one system-wide reference signal, the patent combines what would otherwise require multiple separate phase control circuits into a single shared resource, reducing overall system complexity while maintaining phase alignment
2Reliability
If frequent recalibration is performed to maintain phase stability over temperature variations, then phase coherence is improved, but productivity and system availability deteriorate
Solution Approach 1:
The patent implements preliminary phase alignment by locking all PLLs to a system-wide reference signal before operation begins. This preliminary synchronization establishes deterministic phase relationships that remain stable over temperature variations and power cycles, eliminating the need for frequent recalibration and allowing the system to maintain phase coherence throughout operation without interruption
Solution Approach 2:
The patent uses feedback from the system-wide reference signal to continuously maintain phase alignment. By having all PLLs locked to the same reference signal with deterministic phase relationships, the system creates a feedback mechanism that maintains phase coherence automatically without requiring external recalibration, thus improving both reliability and productivity
3Adaptability or versatility
If multiple dedicated PLLs are distributed across multiple microchips to generate RF clocks, then adaptability and system scalability are improved, but maintaining phase coherence across chips becomes more difficult
Solution Approach 1:
The patent implements a universal system-wide reference signal that serves all PLLs across multiple microchips. This single reference signal performs the function of phase synchronization for all distributed PLLs, allowing the system to scale to multiple chips and antennas while maintaining phase coherence through a unified reference rather than chip-specific references
Data Source
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AI summary
A frequency synthesizer and a method for generating an RF clock signal. A system includes a plurality of transceivers. Each transceiver includes a digital-to-analog converter, an analog-to-digital converter, and a frequency synthesizer. A frequency synthesizer in each transceiver receives a first reference clock signal and a second, different, reference clock signal. The frequency synthesizer includes a digitally-controlled oscillator (DCO), a feedback loop circuitry, a phase alignment and clock generation circuitry. The DCO generates an RF clock signal that is synchronized with the first reference clock signal. The phase alignment and clock generation circuitry aligns the phase of the RF clock signal with a phase of the second reference clock signal. The second reference clock signal is a system-wide reference clock signal for the plurality of transceivers.