RF Circuit Clock Switching to Mitigate Digital Interference

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Solution Overview

Problem

Current solutions to mitigate radio frequency interference from digital activity in integrated circuits are complex and adversely affect high digital communication bandwidth.

Innovation Solution

A system that dynamically selects between an LO-derived clock signal and a source clock signal for digital circuitry based on radio activity, using a controller to switch between these signals to minimize interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If digital circuitry and RF circuitry are located within the same integrated circuit, then integration and miniaturization are improved, but digital activity interferes with RF communication

Engineering Contradiction:
Improveintegrated circuit areaVSAvoiddigital interference to RF communication
Core Design Contradiction:
Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

The patent dynamically switches the clock signal source for digital circuitry between a source clock signal and an LO-derived clock signal based on RF activity state. When RF circuitry is active, the system uses the LO-derived clock signal to synchronize digital activity with RF operation, thereby reducing digital interference while maintaining integration benefits.

Inventive Principle:
Principle #15Dynamics

2Reliability

If current solutions are used to reduce radio interference, then RF communication reliability is improved, but digital communication bandwidth is adversely affected

Engineering Contradiction:
ImproveRF communication reliabilityVSAvoiddigital communication bandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system dynamically adjusts clock signal selection based on RF activity detection. When RF communication is active, it switches to LO-derived clocking to ensure RF reliability. When RF is inactive, it switches to source clock signal to maximize digital communication bandwidth, thus resolving the trade-off between reliability and productivity.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the clock frequency parameter of digital circuitry by selecting different clock sources. The LO-derived clock signal has a frequency derived from the LO clock signal, while the source clock signal operates at a different frequency optimized for digital communication, allowing the system to adapt parameters based on operational mode.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If digital circuitry operates at high clock frequencies, then digital communication bandwidth is improved, but interference with RF circuitry increases

Engineering Contradiction:
Improvedigital communication bandwidthVSAvoiddigital interference to RF circuitry
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The system dynamically changes the clock frequency parameter by switching between two clock sources. When RF activity is detected, it transitions to the LO-derived clock signal which operates at a frequency that minimizes interference with RF circuitry, while still allowing digital communication to function. This dynamic parameter adjustment resolves the contradiction between high bandwidth operation and interference reduction.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12567943B2Mitigating digital interference within radio frequency circuitry
Publication Date: 2026.03.03 SILICON LABORATORIES INC
  • US12567943B2 patent drawing
  • US12567943B2 patent drawing
  • US12567943B2 patent drawing

AI summary

In one aspect, an apparatus includes: radio frequency (RF) circuitry to transmit and receive RF signals, the RF circuitry to operate with a local oscillator (LO) clock signal; clock circuitry to receive the LO clock signal and generate an LO-derived clock signal therefrom; first digital circuitry to communicate data according to a first digital clock signal; and a controller coupled to the first digital circuitry to select one of the LO-derived clock signal or a source clock signal to provide to the first digital circuitry as the first digital clock signal.