RF Clock Generation With Double Clipping and Spurious Tone Cancellation
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Solution Overview
Problem
In RF communication systems, generating multiple RF clock signals using phase-locked-loops (PLLs) can lead to interference and degradation of performance due to the complexity of integrating multiple PLLs within a single chip, resulting in undesirable modulation and harmonic tones in the output signal.
Innovation Solution
A clock generator circuit that includes an up-converter, band-pass filter, and spurious tone cancellation circuit to produce high-quality RF clock signals by detecting and canceling unwanted tones, allowing for the generation of multiple RF clock signals without the need for additional PLLs, using a single PLL for both transmitter and receiver circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple PLLs are integrated into a single chip to generate multiple RF clock signals, then the quantity of RF clock signals increases, but the device complexity increases and interference between PLLs degrades performance
Solution Approach 1:
The patent merges the functionality of multiple PLLs into a single PLL by using one PLL to generate a master RF clock signal that is then distributed and divided to create multiple clock signals for different communication standards, thereby reducing device complexity and eliminating inter-PLL interference while maintaining the ability to generate multiple RF clock signals
Solution Approach 2:
The single PLL is designed to serve multiple functions by generating a master clock signal that can be divided and configured to support multiple RF communication standards (GSM, WCDMA, Bluetooth, LTE, etc.), making the PLL universal and eliminating the need for separate dedicated PLLs for each standard
2Device complexity
If an up-converter is used to generate additional RF clock signals without adding new PLLs, then the device complexity decreases, but spurious tones are generated that degrade signal quality
Solution Approach 1:
The patent converts the harmful spurious tones generated by the up-converter into beneficial cancellation signals by detecting these tones and generating inverted versions that are added back to the output signal, thereby canceling the spurious tones and improving signal quality while maintaining the simplicity of using a single PLL
3Manufacturing precision
If spurious tone cancellation is implemented by detecting and canceling unwanted tones, then the signal quality improves, but the device complexity increases
Solution Approach 1:
The patent implements feedback by detecting spurious tones in the output signal and using this information to generate cancellation signals that are fed back into the output to eliminate the detected tones, creating a closed-loop system that automatically improves signal quality through continuous monitoring and correction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces unwanted tones in the output signal, improving the quality of RF clock signals and enabling efficient generation of multiple RF clock signals without degrading performance, suitable for various wireless communication standards like GSM, WCDMA, Bluetooth, and LTE.
Implementation Method 1
an up-converter to up-convert modulation signals and quadrature local radio frequency clock signals to obtain an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal
Implementation Method 2
a band pass filter to filter the up-converted signal and output a filtered version of the up-converted signal
Implementation Method 3
a first clock driver/divider to amplify and clip the filtered version of the up-converted signal to obtain a first-clipped clock signal
Implementation Method 4
a tone detection circuit to detect a residual error signal of one or more unwanted tones in a compensated version of the first-clipped clock signal
Implementation Method 5
a coupler to couple the cancellation tones to the first-clipped clock signal to obtain the compensated version of the first-clipped clock signal
Data Source
AI summary
A clock generator circuit generates a wanted RF clock signal by using an up-converter, a spurious tone cancellation circuit, a controller, and at least two clock driver/dividers. The spurious tone cancellation circuit includes a tone detection circuit and a tone generation circuit. The up-converter mixes modulation signals with local quadrature RF clock signals to create an up-converted signal having a frequency tone equal to a desired frequency of the wanted RF clock signal. The first clock driver/divider amplifies and clips the up-converted signal into a first-clipped clock signal. The tone detection circuit detects the amplitude and phase of unwanted tones of the first-clipped clock signal in the baseband domain and provides information to the controller, which controls the tone generation circuit to cancel the unwanted tones and create a compensated version of first-clipped clock signal. The second clock driver/divider further amplifies and clips the compensated version of first-clipped clock signal to generate the wanted RF clock signal.