RF-CMOS Transistor Array with Shared Body Contact
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Solution Overview
Problem
RF-CMOS transistors face issues with parasitic series resistance due to large body connection rings, non-uniform current flow caused by varying polysilicon gate linewidths, and challenges in the photolithographic process due to grille patterns leading to diffraction, resulting in performance degradation and reliability concerns.
Innovation Solution
The solution involves breaking down the RF-CMOS device into sections or cells with a substrate connection grid and using dummy polysilicon lines to create a uniform grille, reducing parasitic resistance and ensuring uniform current flow by minimizing the distance to body connections and optimizing the manufacturability of gate polysilicon lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large body connection ring is used to surround the active area, then the body connection is provided, but the distance to innermost parts increases resulting in significant series resistance
Solution Approach 1:
The body connection ring is segmented into discrete body contact regions distributed around the active area, with each segment providing local body connection. This reduces the distance from any point in the active area to the nearest body contact, thereby reducing parasitic series resistance while maintaining complete body coverage.
2Ease of manufacture
If polysilicon gates are arranged as parallel stripes, then the gate structure is formed, but outer stripes have different local environment causing non-uniform linewidth and current flow
Solution Approach 1:
Dummy polysilicon lines are added at the outer edges of the gate grille to create a uniform local environment for all polysilicon lines during photolithography and etching processes. This ensures that outer gate stripes experience the same optical and chemical conditions as inner stripes, resulting in uniform linewidth and current distribution across all gate fingers.
3Reliability
If multiple gate connections are employed to minimize gate series resistance, then RF-CMOS performance is optimized, but device complexity increases
Solution Approach 1:
Multiple gate connection sites are merged into shared polysilicon regions that serve multiple gate fingers simultaneously. This reduces the total number of separate connections while maintaining low gate series resistance, as the shared regions provide efficient electrical pathways to multiple gates without requiring individual connections for each finger.
Data Source
AI summary
An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate.