Direct RF Complex ADC Calibration for Channel Imbalance Correction

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Solution Overview

Problem

Existing complex analog to digital converters (CADCs) face issues with amplitude and phase imbalances between ADC channels and clock skew errors, leading to distorted filter responses and insufficient spurious free dynamic range (SFDR), particularly in high-end applications like radar and communications.

Innovation Solution

A direct RF CADC system that applies phase and amplitude corrective factors to complex bandpass filter coefficients to account for imbalances, using a method that calculates these factors based on measured phase and amplitude differences between ADC channels, and employs a second stage filter to cancel harmonics and produce corrected in-phase and quadrature outputs at baseband.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If time-interleaved low speed ADCs are used to reduce sampling rate requirements, then device complexity and cost are reduced, but amplitude and phase imbalances between ADC channels cause distorted filter response and reduced SFDR

Engineering Contradiction:
ImproveADC speed requirementsVSAvoidfilter response consistency
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by calculating corrective factors for amplitude and phase imbalances and applying them to filter coefficients. This dynamically adjusts the filter parameters to compensate for ADC channel variations, resolving the contradiction between using lower-precision time-interleaved ADCs and maintaining filter response consistency.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback by measuring the actual amplitude and phase responses of each ADC channel and using these measurements to compute corrective factors. This closed-loop approach continuously compensates for manufacturing variations, allowing the use of less precise ADCs while maintaining overall system performance.

Inventive Principle:
Principle #23Feedback

2Ease of manufacture

If standard ADC hardware is used without correction, then manufacturing tolerances are easier to meet, but clock skew errors and amplitude/phase imbalances result in distorted filter response and insufficient SFDR

Engineering Contradiction:
ImproveADC channel matchingVSAvoidSFDR performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent converts the harmful effects of amplitude and phase imbalances into beneficial corrections by measuring these imbalances and applying corrective factors. The very imperfections that arise from easier manufacturing processes are quantified and used to generate compensation parameters, turning a disadvantage into an advantage.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

By changing the filter coefficients based on measured ADC characteristics, the system compensates for manufacturing tolerances. This parameter adjustment allows standard ADC hardware to achieve high SFDR performance that would otherwise require tightly controlled manufacturing.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If corrective factors are applied to filter coefficients to compensate for ADC imbalances, then filter response consistency and SFDR are improved, but additional signal processing complexity is introduced

Engineering Contradiction:
Improvefilter response consistencyVSAvoidsignal processing requirements
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The corrective factors are calculated in advance during a calibration phase and stored for use during normal operation. This preliminary computation of correction parameters reduces the real-time processing complexity, as the heavy computational burden is performed offline rather than during signal conversion.

Inventive Principle:
Principle #10Preliminary action

4Speed

If ADCs operate at lower sampling rates using time-interleaving, then lower speed and power consumption are achieved, but harmonics produced by ADCs reduce SFDR to levels insufficient for high-end applications

Engineering Contradiction:
ImproveADC sampling rateVSAvoidharmonic distortion
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and removes harmful harmonic components from the ADC output by applying corrective filtering. The filter design specifically targets and eliminates harmonics generated by the time-interleaved ADC operation, allowing lower sampling rates to be used without compromising SFDR performance.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS8836552B1Direct input radio frequency complex analog to digital converter with corrective factors
Publication Date: 2014.09.16 LOCKHEED MARTIN CORP
  • US8836552B1 patent drawing
  • US8836552B1 patent drawing
  • US8836552B1 patent drawing

AI summary

A direct radio frequency complex analog to digital converter (CADC) device provides corrective factors including a plurality of time-interleaved low speed ADCs, wherein each ADC corresponds to an ADC channel. A phase corrective factor is calculated for each ADC channel. An amplitude corrective factor is calculated for each ADC channel. The phase and amplitude corrective factors are applied to complex bandpass filter coefficients to produce filter coefficients corrected for the phase and amplitude imbalances between ADCs. Digital output of each ADC channel is filtered by a complex bandpass filter using the corrected filter coefficients to produce corrected in-phase and quadrature output at baseband. Harmonics produced by the ADCs are canceled by filtering ADC outputs in a first bandpass filter to an intermediate frequency such that the harmonics fall outside the band of interest, a second filter is applied to attenuate the harmonic and produce a signal output at baseband.