RF DAC Multiphase Clocking for Third-Harmonic Cancellation
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Solution Overview
Problem
Existing techniques for countering third harmonic distortion (HD3) and third counter intermodulation (CIM3) in RF digital-to-analog converters and digital transmitters are inefficient due to high power consumption and large chip area requirements, particularly with 8-phase clocking and LC filters.
Innovation Solution
The use of multiphase clock pulses with adjustable duty cycles, specifically four-phase clock pulses with 33% or 50% duty cycles, to produce a null at the third harmonic frequency in the frequency spectrum, effectively canceling HD3 and CIM3 without the need for large inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 8-phase clocking is used to counter HD3 and CIM3, then distortion rejection is improved, but power consumption increases
Solution Approach 1:
The patent changes the duty cycle parameter of the clock pulses from the conventional 50% to specific values (33% or 67%) to achieve HD3 cancellation. This parameter modification allows the system to achieve the same distortion rejection performance with reduced power consumption by using fewer clock phases.
Solution Approach 2:
The patent extracts and eliminates the need for large inductor components by using a capacitive-based duty cycle modulation approach. This removes the power-hungry inductor-based LC filters while maintaining the HD3 rejection capability through duty cycle-controlled clock pulses.
2Reliability
If LC filters tuned at 3f LO are used to counter HD3 and CIM3, then distortion rejection is improved, but chip area increases due to large inductors
Solution Approach 1:
The patent extracts and removes the large inductor components from the circuit by replacing the inductor-based LC filter approach with a capacitor-based duty cycle modulation method. This eliminates the need for large on-chip inductors while maintaining the same frequency-selective filtering function for HD3 rejection.
Solution Approach 2:
The patent substitutes the mechanical/physical inductor component with an electronic control mechanism based on duty cycle modulation of clock pulses. This replaces the passive inductor-based filtering with an active duty cycle-controlled switching approach that achieves the same frequency rejection without requiring physical inductors.
3Reliability
If duty cycle is adjusted to produce null at third harmonic frequency, then HD3 and CIM3 rejection is improved, but clock signal complexity increases
Solution Approach 1:
The patent modifies the duty cycle parameter of existing clock phases to achieve HD3 cancellation. By adjusting the duty cycle of the available clock phases (without adding new phases), the system creates a spectral null at the third harmonic frequency while keeping the clock generation logic relatively simple.
Data Source
Figure 1
Figure 2A~2C
Figure 3A~3D
AI summary
A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.