RF DAC Multiphase Pulse Duty Cycling for HD3 Cancellation

The patent changes the duty cycle parameter of the clock signal from conventional values (e.g., 50%) to a specific value of approximately 33.3% (1/3). This parameter change creates a null in the frequency spectrum at the third harmonic frequency (3fLO), thereby rejecting HD3 and CIM3 distortion products without requiring additional filtering components or increased power consumption. The duty cycle modification directly achieves distortion rejection while maintaining low power consumption and small chip area.

The patent modifies the duty cycle parameter to approximately 33.3% (1/3), which creates a spectral null at the third harmonic frequency. This approach eliminates the need for physical LC filters and their associated large inductors, achieving distortion rejection through timing and duty cycle control rather than through large passive components. The result is significantly reduced chip area while maintaining effective HD3 and CIM3 rejection.

The patent implements a straightforward duty cycle adjustment to approximately 33.3% (1/3) of the clock period. This simple parameter change can be implemented by adjusting the pulse width generator or clock signal generation circuitry without adding complex filtering stages, multiple clock phases, or additional components. The low complexity arises from the fact that only the duty cycle parameter needs to be modified, while the overall system architecture remains unchanged.