RF DAC Shadow Switching for HD2 and Crosstalk Reduction
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs), particularly radio frequency (RF) DACs, face challenges in reducing common mode switching glitches due to second-order performance spur folding, which degrades performance at higher frequencies and is not effectively addressed by existing techniques such as extreme make-before-break switching.
Innovation Solution
The implementation of shadow capacitor switching in DAC current steering cells, where shadow transistors are used to either cancel or augment glitch energy in bleeder current paths, allowing for improved harmonic distortion and cross-talk performance by introducing additional switching energy at specific frequencies, thereby reducing common mode glitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switching techniques are used in RF DACs, then the circuit complexity is low, but common mode switching glitches and HD2 spurs are generated that degrade performance at higher frequencies
Solution Approach 1:
The patent divides the current steering path into multiple segments by introducing shadow capacitor switching cells that operate in parallel with the main switching path. This segmentation allows the glitch energy to be distributed and managed separately, improving spurious performance without requiring complete redesign of the entire DAC circuit.
Solution Approach 2:
The patent introduces shadow capacitors and shadow switching transistors as intermediary elements between the digital input and the analog output. These intermediary components capture and redirect the glitch energy that would otherwise appear as HD2 spurs, effectively mediating the switching process to reduce common mode glitches while maintaining circuit functionality.
2Object-generated harmful factors
If extreme make-before-break switching is used to reduce glitches, then common mode switching glitches are reduced, but charge loss increases which is directly proportional to the output frequency
Solution Approach 1:
The patent extracts the glitch-generating switching operation from the main current path by using shadow capacitors that are switched in parallel. This separation allows the switching glitches to be captured and managed independently in the shadow path, preventing them from appearing as common mode glitches at the output while avoiding the charge loss associated with extreme make-before-break switching in the main path.
3Measurement precision
If shadow capacitor switching is implemented, then HD2 and cross-talk performance is improved, but the device complexity increases due to additional transistors and capacitors
Solution Approach 1:
The patent merges the shadow capacitor switching functionality with the existing DAC current steering cell structure. By integrating the shadow switching transistors and capacitors into the regular DAC architecture, the patent achieves improved HD2 and cross-talk performance while minimizing the increase in overall device complexity through shared circuit elements and compact layout.
Data Source
AI summary
A DAC cell includes first and second transistors, drain-source coupled at a first node, a gate of the second transistor coupled to a data input (D), and third and fourth transistors, drain-source coupled at a second node, a gate of the fourth transistor coupled to a complement of the data input (DB). The circuit further includes first and second shadow transistors each coupled between the first node and ground, a gate of the first shadow transistor coupled to a switching input (S) and a gate of the second shadow transistor coupled to a complement of the switching input (SB). The circuit still further includes third and fourth shadow transistors each coupled between the second node and ground, a gate of the third shadow transistor coupled to S and a gate of the fourth shadow transistor coupled to SB.