RF DAC Switch Driver Architecture for Low-Distortion Output
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Solution Overview
Problem
High-speed digital-to-analog converters (DACs) face challenges with distortion and high power consumption due to code-dependent glitching, especially at high frequencies, which affects their linear output and efficiency.
Innovation Solution
The implementation of a dual and tri-level switch drive system with positive feedback circuitry and XOR operations in the switch drivers, enabling current steering and reducing latency, while operating in saturation regions to minimize noise and distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional switch drive circuits are used in high-speed DACs, then the circuit complexity is low, but code-dependent glitching causes distortion and high power consumption at high frequencies
Solution Approach 1:
The switch driver is segmented into multiple independent latches (first latch, second latch, third latch) that process different portions of the input signal simultaneously. This segmentation allows parallel processing of signal paths, reducing code-dependent interactions and minimizing glitching while maintaining manageable complexity in each individual latch unit.
Solution Approach 2:
The patent transitions from a single-level switch drive to a multi-level architecture where latches operate at different hierarchical levels. The first latch processes the most significant bits, the second latch processes intermediate bits, and the third latch processes least significant bits, creating a dimensional hierarchy that reduces code-dependent glitching across the full signal range.
2Speed
If high-speed operation is implemented in DACs, then the operating frequency increases, but power consumption increases linearly with frequency
Solution Approach 1:
The patent implements periodic reset of all latches synchronized to the clock signal edges. The first latch resets on rising edges, the second latch resets on falling edges, and the third latch resets on rising edges, creating a periodic action pattern that efficiently manages power consumption at high frequencies by systematically clearing floating nodes at regular intervals.
Solution Approach 2:
Positive feedback paths are implemented within each latch to rapidly establish stable output states. The feedback mechanisms include cross-coupled transistors that reinforce the latch state, reducing the time required for settling and minimizing the duration of high-power transient states during switching operations.
3Reliability
If conventional latches are used, then floating nodes cause code-dependent glitching, but adding reset mechanisms increases circuit complexity
Solution Approach 1:
Reset mechanisms are activated in advance of potential glitch conditions by synchronizing latch resets to specific clock signal edges. The first latch is reset before processing new data on rising edges, the second latch is reset before processing on falling edges, and the third latch is reset before processing on rising edges, preventing floating node conditions before they can cause glitches.
Solution Approach 2:
The patent changes the operational parameters of latches by implementing different reset timing for different latch levels. The first and third latches use rising-edge-triggered resets while the second latch uses falling-edge-triggered resets, creating parameter differentiation that systematically eliminates floating nodes without requiring identical complex reset circuitry in all latches.
Data Source
AI summary
A digital-to-analog converter (DAC) capable of operating in radio frequency (RF) with linear output, low distortion, low power consumption, and input data independence. The DAC includes switch drivers and output switches driven by the switch drivers. The switch drivers include pairs of outputs, and positive feedback circuitries coupled between respective pairs of outputs. The output switches are arranged between a first current source configured to push current to the DAC's outputs and a second current source configured to pull current from the DAC's outputs. Different output switches are configured to push current to and pull current from the DAC's outputs in accordance with rising edges and falling edges, respectively.