RF Current Steering DAC With XOR Clocking for Fewer Switches

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Solution Overview

Problem

Current RF current steering digital-to-analog converters (DACs) face challenges with increased area and power consumption due to additional switches required for constant switching activity, which affects dynamic performance and efficiency.

Innovation Solution

The implementation of a current steering DAC with a source-coupled transistor pair, a current source, and combinatorial logic that performs an exclusive OR operation on data and clock signals, reducing the number of switches needed and eliminating the need for a mixer in the signal chain, thereby minimizing parasitic capacitance and improving settling time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If additional switches are added to ensure constant switching activity on the drain of the current source, then code independent dynamic performance is achieved, but area and power consumption increase

Engineering Contradiction:
Improvedynamic performanceVSAvoidarea
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic switching activity by using a clock signal that alternately activates different sets of switches in different time periods. During first time periods, first switches are activated while second switches remain inactive, and during second time periods, the activation is reversed. This dynamic time-multiplexed approach ensures that switching activity occurs on the drain of the current source while using fewer total switches, thereby achieving code-independent dynamic performance without proportionally increasing area.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs periodic switching controlled by a clock signal that alternates between different switching configurations in regular time intervals. The clock signal has alternating first and second time periods that periodically activate different switch sets, ensuring continuous switching activity on the current source drain while reducing the total number of switches needed compared to simultaneous activation schemes.

Inventive Principle:
Principle #19Periodic action

2Reliability

If additional switches are added to ensure constant switching activity on the drain of the current source, then code independent dynamic performance is achieved, but power consumption increases

Engineering Contradiction:
Improvedynamic performanceVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent implements dynamic switching activity by using a clock signal that alternately activates different sets of switches in different time periods. During first time periods, first switches are activated while second switches remain inactive, and during second time periods, the activation is reversed. This dynamic time-multiplexed approach ensures that switching activity occurs on the drain of the current source while using fewer total switches, thereby achieving code-independent dynamic performance without proportionally increasing power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs periodic switching controlled by a clock signal that alternates between different switching configurations in regular time intervals. The clock signal has alternating first and second time periods that periodically activate different switch sets, ensuring continuous switching activity on the current source drain while reducing the total number of switches needed compared to simultaneous activation schemes.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If a mixer is added to translate the analog signal to a carrier frequency, then RF output is achieved, but device complexity increases

Engineering Contradiction:
ImproveRF output capabilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the functions of the DAC and the mixer into a single integrated device. The current steering DAC directly generates RF output signals at desired carrier frequencies by using clocked switching that modulates the current output according to the digital input codes and clock signal. This integration eliminates the need for a separate mixer stage, thereby achieving RF output capability while reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements a multi-functional DAC that can directly generate RF signals at various carrier frequencies without requiring external mixing components. The clocked current steering mechanism provides both digital-to-analog conversion and frequency translation functions within the same device, making it a universal solution that replaces multiple separate components.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9432036B1Radio frequency current steering digital to analog converter
Publication Date: 2016.08.30 XILINX INC
  • US9432036B1 patent drawing
  • US9432036B1 patent drawing
  • US9432036B1 patent drawing

AI summary

In one example, a current steering circuit for a digital-to-analog converter (DAC) includes a source-coupled transistor pair responsive to a differential gate voltage; a current source coupled to the source-coupled transistor pair operable to source a bias current; a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage; a driver having a first input, a second input, and a differential output, the differential output providing the differential gate voltage; and combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively OR a data signal on the data input and a clock signal on the clock input.