RF Time Delay Circuit Using Shunt Switching to Cut Insertion Loss
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Solution Overview
Problem
Traditional time delay units (TDUs) in RF and microwave systems suffer from high insertion loss due to the use of series transistors in the delay path, which degrades signal quality and efficiency, especially in high-frequency applications.
Innovation Solution
The proposed TDU architecture employs shunt transistors in conjunction with impedance inverters to switch RF signals between reference and delay paths, eliminating series transistors in the delay path and utilizing Coff resonators to minimize insertion loss, while supporting monolithic integration with amplifiers and detectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If series transistors are used in the delay path to switch RF signals, then the switching function is achieved, but insertion loss increases significantly
Solution Approach 1:
The patent inverts the traditional switching topology by replacing series transistors with shunt transistors in the delay path. Instead of switching the signal through a series transistor (which introduces resistance and loss), the signal flows through a shunt transistor configuration where the transistor is placed in parallel with the signal path. When the shunt transistor is OFF, the signal passes through with minimal loss; when ON, it directs the signal through the delay path. This inversion of the switching topology fundamentally resolves the insertion loss problem while maintaining reliable signal switching.
Solution Approach 2:
The patent introduces impedance inverters as intermediary components between the shunt transistors and the signal path. These impedance inverters act as mediators that transform the impedance seen by the signal, enabling the shunt transistor to effectively switch the signal between reference and delay paths without introducing significant loss. The impedance inverter serves as an intermediary that adapts the shunt transistor's switching action to the RF signal path, resolving the contradiction between switching functionality and signal quality.
2Loss of energy
If shunt transistors are used in the delay path, then insertion loss is reduced, but the switching mechanism becomes more complex
Solution Approach 1:
The patent employs a unified shunt transistor switching mechanism that serves multiple functions simultaneously. The same shunt transistor configuration is used to achieve both signal switching between paths and impedance transformation through the associated inverter circuits. This multi-functional approach reduces overall device complexity compared to using separate components for each function, as the shunt transistor structure inherently supports both switching and impedance adaptation roles.
Solution Approach 2:
The patent merges the switching function and the impedance transformation function into a single integrated structure. The shunt transistor is combined with the impedance inverter in a unified configuration where both functions are achieved through the same physical components working together. This merging eliminates the need for separate switching and impedance matching circuits, thereby reducing overall device complexity while maintaining low insertion loss.
3Device complexity
If series transistors are used for switching, then the circuit structure is simple, but signal quality degrades due to resistive losses
Solution Approach 1:
The patent inverts the traditional series transistor switching approach by using shunt transistors instead. This inversion changes the fundamental topology from series to parallel configuration, which inherently reduces resistive losses in the signal path. The shunt transistor, when OFF, presents a high impedance path that does not interfere with the signal, and when ON, provides a low-impedance path to ground that effectively switches the signal without introducing series resistance. This topological inversion resolves the contradiction between structural simplicity and signal quality.
4Loss of energy
If Coff resonators are added to resonate with off-state capacitance, then insertion loss is minimized, but device complexity increases
Solution Approach 1:
The patent utilizes parameter changes by introducing Coff resonators that are specifically tuned to resonate with the off-state capacitance of the shunt transistors at the operating frequency. By adjusting the resonator parameters (inductance and capacitance values) to match the transistor's off-state capacitance, the system achieves resonance that cancels out the capacitive effect, thereby minimizing insertion loss. This parameter-matching approach allows the addition of resonators to be offset by the performance improvement, making the increased complexity worthwhile.
Solution Approach 2:
The patent converts the harmful effect of the transistor's off-state capacitance (which causes insertion loss) into a beneficial resonance condition. By adding Coff resonators that resonate with this previously problematic capacitance, the system transforms the capacitance from a source of loss into a resonant element that improves performance. The off-state capacitance, which was originally harmful, becomes a useful component of the resonant circuit, thereby converting harm into benefit and justifying the added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces insertion loss, optimizes system performance, and enables efficient integration of TDUs in advanced RF and microwave systems by leveraging shunt transistors and impedance inverters, enhancing signal quality and efficiency.
Implementation Method 1
When the shunt transistor (Q1) in the delay path is turned 'OFF' it looks like a very low loss capacitor which can be resonated with a Coff resonator
Implementation Method 2
The delay path includes a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor
Data Source
AI summary
A time delay circuit includes a first port, a second port, a reference path coupled between the first and second ports, a delay path coupled between the first and second ports, and a control circuit configured to activate one of the reference path and the delay path. The reference path includes a series transistor and a first inductor connected in parallel with the series transistor. The delay path includes a first shunt transistor, a second inductor connected in parallel with the first shunt transistor, and a first impedance inverter coupled between the first port and the first shunt transistor.