Programmable RF Delay Circuit Using Switched Capacitor Banks
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Solution Overview
Problem
Current RF delay devices are unable to provide programmable delays exceeding 100 ns over a broad bandwidth, which is essential for full-duplex RF wireless systems and other applications, as they are limited by narrow bandwidth and lack of programmability in existing acoustic delay lines and other solutions.
Innovation Solution
A programmable delay device utilizing M sampling switched capacitor storage elements and M×N programmable switched capacitor banks, reducing sampling rate and enabling longer delays with reduced leakage current, and including an output reconstruction stage to generate a delayed RF signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If acoustic delay lines are used to achieve >100 ns of RF delay, then delay time is improved, but bandwidth becomes narrow and programmability is lost
Solution Approach 1:
The delay device is segmented into multiple stages, each implementing a portion of the total delay. This segmentation allows the overall system to achieve >100 ns delay while maintaining bandwidth and programmability through the distributed architecture of multiple manageable delay stages.
Solution Approach 2:
The invention changes the operating parameters by using switched capacitor circuits with programmable division ratios (M and N) to achieve variable delay times. This parameter-based control enables programmable delay adjustment while maintaining broad bandwidth, overcoming the fixed-delay limitation of acoustic delay lines.
2Duration of action of moving object
If sampling rate is reduced at individual storage elements to enable longer delays, then delay time is improved, but leakage current increases
Solution Approach 1:
The delay path is segmented into multiple stages with M×N total storage elements. By distributing the total delay across many small steps rather than using a single long delay element, each individual storage element operates at a manageable sampling rate, minimizing leakage current while achieving cumulative delays exceeding 100 ns.
Solution Approach 2:
Switched capacitor circuits serve as intermediary elements between stages, enabling precise control of signal transfer timing. These intermediaries allow the system to maintain low leakage current by using fast switching operations at each stage while still achieving long overall delay through the cascaded architecture.
3Duration of action of moving object
If more delay stages are added to increase delay range, then delay time is improved, but device area increases
Solution Approach 1:
Multiple delay stages are merged into a unified switched capacitor architecture where M sampling storage elements and N delay storage elements work together in an integrated fashion. This merging allows the system to achieve >100 ns delay in a compact form factor by sharing common circuitry and control mechanisms across all stages.
Solution Approach 2:
The switched capacitor storage elements serve multiple functions: they act as both sampling elements and delay elements across different stages. This multi-functionality reduces the total number of separate components needed, thereby minimizing device area while still achieving the required delay range exceeding 100 ns.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves delays exceeding 100 ns over a broad bandwidth (>500 MHz), improving area efficiency and enabling effective RF cancellation in full-duplex wireless systems and other applications.
Implementation Method 1
an input stage that employs M sampling switched capacitor storage elements such that while the input RF signal is sampled at a frequency FS, each individual sampling switched capacitor storage element samples at a rate of only FS/M
Implementation Method 2
M sampling switched capacitor storage elements
Implementation Method 3
each delay switched capacitor storage element sampling and holding a corresponding time interleaved portion of a corresponding input sampled signal
Implementation Method 4
M×N delay switched capacitor storage elements
Implementation Method 5
an output reconstruction stage that reconstructs a programmably delayed version of the input RF signal by reconstructing signals from the programmable delay stage
Data Source
AI summary
A programmable delay device that provides delays of more than 100 ns over a broad bandwidth is disclosed. The device includes an input stage that employs M sampling switched capacitor elements such that each sampling switched capacitor element samples at a rate of only 1/M of the fundamental sampling rate. The device includes a programmable delay stage with M programmable switched capacitor banks, each programmable switched capacitor bank having N delay switched capacitor storage elements. Thus, the programmable delay stage includes a total of M×N delay switched capacitor storage elements, thereby reducing the sampling rate by a factor of M×N. This reduced sampling rate permits much smaller sampling switches, resulting in reduced leakage current and enabling far longer programmable delay times. Lastly, the device includes an output reconstruction stage that reconstructs a delayed version of the input RF signal by combining signals from the programmable delay stage.